[Yosys+Odin]: passing all circuit names at once to Yosys frontend to …

…avoid deleting submodules [Infra]: avoid Surelog and Yosys-F4PGA-Plugins to be compiled with every make call Signed-off-by: Seyed Alireza Damghani <[email protected]>
verilog-to-routing · Aug 15, 2022 · b9c201d · b9c201d
1 parent 17337fe
commit b9c201d
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Showing 3 changed files with 12 additions and 13 deletions.
diff --git a/ODIN_II/SRC/YYosys.cpp b/ODIN_II/SRC/YYosys.cpp
@@ -265,22 +265,24 @@ void YYosys::execute() {
  } else {
  // Read the hardware decription Verilog circuits
  // FOR loop enables include feature for Yosys+Odin (multiple Verilog input files)
- for (auto circuit : this->verilog_circuits) {
+ std::string aggregated_circuits;
+ for (auto circuit : this->verilog_circuits)
+ aggregated_circuits += circuit + " ";
  // Read Verilog/SystemVerilog/UHDM files based on their type, considering the SystemVerilog/UHDM plugins
 # ifdef YOSYS_SV_UHDM_PLUGIN
  /* Load SystemVerilog/UHDM plugins in the Yosys frontend */
  switch (configuration.input_file_type) {
  case (file_type_e::_VERILOG): // fallthrough
  case (file_type_e::_VERILOG_HEADER): {
- run_pass(std::string("read_verilog -sv -nolatches " + circuit));
+ run_pass(std::string("read_verilog -sv -nolatches " + aggregated_circuits));
  break;
  }
  case (file_type_e::_SYSTEM_VERILOG): {
- run_pass(std::string("read_systemverilog -debug" + circuit));
+ run_pass(std::string("read_systemverilog -debug " + aggregated_circuits));
  break;
  }
  case (file_type_e::_UHDM): {
- run_pass(std::string("read_uhdm -debug" + circuit));
+ run_pass(std::string("read_uhdm -debug " + aggregated_circuits));
  break;
  }
  default: {
@@ -289,9 +291,8 @@ void YYosys::execute() {
  }
  }
 # else
- run_pass(std::string("read_verilog -sv -nolatches " + circuit));
+ run_pass(std::string("read_verilog -sv -nolatches " + aggregated_circuits));
 # endif
- }
  // Check whether cells match libraries and find top module
  if (global_args.top_level_module_name.provenance() == argparse::Provenance::SPECIFIED) {
  run_pass(std::string("hierarchy -check -top " + global_args.top_level_module_name.value() + " -purge_lib"));

diff --git a/libs/EXTERNAL/CMakeLists.txt b/libs/EXTERNAL/CMakeLists.txt
@@ -65,8 +65,7 @@ if(${ODIN_USE_YOSYS} OR ${WITH_YOSYS})
  LOG_CONFIGURE ON
  LOG_OUTPUT_ON_FAILURE ON
 
- # usefull flags 
- ALWAYS TRUE 
+ # dependency
  DEPENDS yosys 
  ) 
 
@@ -98,8 +97,7 @@ if(${ODIN_USE_YOSYS} OR ${WITH_YOSYS})
  LOG_CONFIGURE ON
  LOG_OUTPUT_ON_FAILURE ON
 
- # usefull flags 
- ALWAYS TRUE 
+ # dependency
  DEPENDS surelog yosys 
  ) 
  endif() 

diff --git a/vtr_flow/scripts/python_libs/vtr/odin/odin.py b/vtr_flow/scripts/python_libs/vtr/odin/odin.py
@@ -11,9 +11,9 @@
 # supported input file type by Odin
 FILE_TYPES = {
  ".v": "verilog",
- ".vh": "verilog",
- ".sv": "verilog",
- ".svh": "verilog",
+ ".vh": "verilog_header",
+ ".sv": "systemverilog",
+ ".svh": "systemverilog_header",
  ".blif": "blif",
 }