-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathcpu.v
225 lines (211 loc) · 8.46 KB
/
cpu.v
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
module CPU16(clk, reset, busy,
address, data_in, data_out, write);
input clk;
input reset;
output reg busy;
output reg [15:0] address;
input [15:0] data_in;
output reg [15:0] data_out;
output reg write;
reg [15:0] regs[0:10]; // 10 16-bit registers
localparam SP = 6;
localparam IP = 7;
localparam zero = 9;
localparam one = 10;
reg [2:0] state; // CPU state
// CPU states
localparam S_RESET = 0;
localparam S_SELECT = 1;
localparam S_DECODE = 2;
localparam S_COMPUTE = 3;
localparam S_DECODE_WAIT = 4;
localparam S_COMPUTE_WAIT = 5;
reg lessThan; // less than flag
reg equal; // equal flag
reg DATA_WAIT;
// for ALU
wire [15:0] Y; // ALU 16-bit output
reg [3:0] aluop; // ALU operation
reg [15:0] opcode; // to decode ALU inputs
wire [3:0] rdest = (opcode[15:12] & 4'h1) ? 4'h0
: (opcode[15:12] & 4'h3) ? 4'h1
: opcode[5:2];
wire [3:0] rsrc = opcode[9:6];
wire Bconst = ~^opcode[11:10] // ALU B = 10 bit constant (for immediate values) else Bload
wire Bload = opcode[11] & (~opcode[10]) // ALU B = data_bus to get data in else a register
ALU alu(
.A(regs[rdest]),
.B(Bconst ? {6'b0, opcode[9:0]}
: Bload ? data_in
: regs[rsrc]),
.Y(Y),
.aluop(aluop));
initial begin
regs[one] = {16{1'b1}};
regs[zero] = 16'b0;
end
always @(posedge clk)
if (reset)
begin
state <= S_RESET;
end
else begin
case(state)
// state 0: reset/begin new
S_RESET: begin
regs[IP] <=16'h0;
write <= 0;
busy <=0;
state <= S_SELECT;
end
// state 1: select opcode address
S_SELECT: begin
write <= 0;
busy <=0;
address <= regs[IP];
regs[IP] <= regs[IP] + 1;
end
// state 2: read/decode opcode
S_DECODE: begin
opcode <= data_in;
casez (data_in)
// 1001aaaabbbb0000 operation (add) A B, A+B->A
// cmp
16'b1001??????????00:
16'b1010??????????00:
// logical neg, AND, OR, XOR
16'b1011??????????00:
16'b1100??????????00:
16'b1101??????????00:
16'b1110??????????00:begin
aluop <= data_in[15:12];
DATA_WAIT <= 0;
state <=S_COMPUTE;
end
// operation A -> mem16[#]
16'b00010???????????:begin
address <= data_in[10:0];
data_out <= regs[0];
write <= 1;
state <= S_SELECT;
end
// operation B -> mem16[#]
16'b00100???????????:begin
address <= data_in[11:0];
data_out <= regs[1];
write <= 1;
state <= S_SELECT;
end
// operation A -> mem16[#]
16'b00011???????????:begin
address <= regs[rsrc];
data_out <= regs[0];
write <= 1;
state <= S_SELECT;
end
// operation B -> mem16[#]
16'b00101???????????:begin
address <= regs[rsrc];
data_out <= regs[1];
write <= 1;
state <= S_SELECT;
end
// opertation lda_ram from mem10[#]
// opertation ldb_ram from mem10[#]
16'b000111??????????:
16'b001111??????????:begin
address <= data_in[9:0];
// load B
aluop <=4'h3;
state <= S_COMPUTE_WAIT;
end
// opertation lda_ram from reg
// opertation ldb_ram from reg
16'b000101????????0?:
16'b001101????????0?:begin
address <= regs[rsrc];
// load B
aluop <= 4'h3;
state <= S_COMPUTE_WAIT;
end
// opertation lda_rom from reg
// opertation ldb_rom from reg
16'b000101????????1?:
16'b001101????????1?:begin
address <= regs[rsrc];
busy <= 1;
// load B
aluop <=4'h3;
state <= S_COMPUTE_WAIT;
end
// operation mv R1 R2, R1 -> R2
16'b0100????????0000:begin
regs[rdest] <= regs[rsrc]
state <= S_SELECT;
end
// operation shift right
16'b100001????????0:begin
aluop <=4'h7;
state <= S_COMPUTE_WAIT;
end
// operation shift left
16'b100001????????1:begin
aluop <=4'h8;
state <= S_COMPUTE_WAIT;
end
// operation jmp mem10[#]
16'b011100?????????:begin
regs[IP] <= data_in[9:0];
state <= S_SELECT;
end
// operation jmp mem16[Reg]
16'b011101????00000:begin
regs[IP] <= regs[rdest];
state <= S_SELECT;
end
// operation beq mem16[Reg]
16'b010101????00000:begin
if (equal):
regs[IP] <= regs[rdest];
state <= S_SELECT;
end
// operation beq mem10[#]
16'b010100?????????:begin
if (equal):
regs[IP] <= data_in[9:0];
state <= S_SELECT;
end
// operation blt mem16[Reg]
16'b011001????00000:begin
if (lessThan):
regs[IP] <= regs[rdest];
state <= S_SELECT;
end
// operation blt mem10[#]
16'b011000?????????:begin
if (lessThan):
regs[IP] <= data_in[9:0];
state <= S_SELECT;
end
endcase
end
// state 3: compute ALU output and flags
S_COMPUTE: begin
// send Y to destination register
regs[rdest] <= Y[15:0];
// set flags
lessThan = Y[15];
equal = Y[14];
state <= S_SELECT;
end
// wait 1 cycle for Data read
S_DECODE_WAIT: begin
state <= S_DECODE;
end
// wait 1 cycle for ALU
S_COMPUTE_WAIT: begin
state <= S_COMPUTE;
end
endcase
end
endmodule