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7 stars written in SystemVerilog
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Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

SystemVerilog 1,468 572 Updated Jan 24, 2025

A directory of Western Digital’s RISC-V SweRV Cores

SystemVerilog 859 132 Updated Mar 26, 2020

The root repo for lowRISC project and FPGA demos.

SystemVerilog 595 148 Updated Aug 3, 2023

Public repository for Litefury & Nitefury

SystemVerilog 280 72 Updated Jun 21, 2024

Open hardware test equipment

SystemVerilog 145 22 Updated Oct 16, 2024

BSODomizer HD: HDL for Cyclone V GX Starter Kit

SystemVerilog 15 3 Updated Aug 5, 2016

Open Source AES

SystemVerilog 1 Updated Feb 18, 2022