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10 stars written in VHDL
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Parallella board design files

VHDL 415 179 Updated Feb 12, 2022

Community created parallella projects

VHDL 390 143 Updated Jun 9, 2019

Open Source 4k CSI-2 Rx core for Xilinx FPGAs

VHDL 389 106 Updated Nov 14, 2018

Two RX-channel 6 GHz FMCW radar design files

VHDL 232 89 Updated May 5, 2023

Original hand-coded firmware for the HDMI2USB - HDMI/DVI Capture - project

VHDL 105 26 Updated Jan 10, 2016

AD9361 based USB3 SDR

VHDL 101 29 Updated Oct 3, 2017

FPGA project to man-in-the-middle attack Flexray

VHDL 79 20 Updated Mar 7, 2020

Vivado design for basic NeTV2 FPGA with chroma-based overlay

VHDL 20 8 Updated Dec 24, 2016

Open JTAG project

VHDL 11 11 Updated Jul 17, 2014

Template to create a custom module / protocol in HARDSPLOIT

VHDL 4 6 Updated Oct 24, 2019