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crossproduct_30.ptx
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crossproduct_30.ptx
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//
// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: CL-23083092
// Cuda compilation tools, release 9.1, V9.1.85
// Based on LLVM 3.4svn
//
.version 6.1
.target sm_30
.address_size 64
// .globl crossproduct
.visible .entry crossproduct(
.param .u64 crossproduct_param_0,
.param .u64 crossproduct_param_1,
.param .u64 crossproduct_param_2,
.param .u64 crossproduct_param_3,
.param .u64 crossproduct_param_4,
.param .u64 crossproduct_param_5,
.param .u64 crossproduct_param_6,
.param .u64 crossproduct_param_7,
.param .u64 crossproduct_param_8,
.param .u32 crossproduct_param_9
)
{
.reg .pred %p<2>;
.reg .f32 %f<16>;
.reg .b32 %r<9>;
.reg .b64 %rd<29>;
ld.param.u64 %rd1, [crossproduct_param_0];
ld.param.u64 %rd2, [crossproduct_param_1];
ld.param.u64 %rd3, [crossproduct_param_2];
ld.param.u64 %rd4, [crossproduct_param_3];
ld.param.u64 %rd5, [crossproduct_param_4];
ld.param.u64 %rd6, [crossproduct_param_5];
ld.param.u64 %rd7, [crossproduct_param_6];
ld.param.u64 %rd8, [crossproduct_param_7];
ld.param.u64 %rd9, [crossproduct_param_8];
ld.param.u32 %r2, [crossproduct_param_9];
mov.u32 %r3, %ctaid.y;
mov.u32 %r4, %nctaid.x;
mov.u32 %r5, %ctaid.x;
mad.lo.s32 %r6, %r4, %r3, %r5;
mov.u32 %r7, %ntid.x;
mov.u32 %r8, %tid.x;
mad.lo.s32 %r1, %r6, %r7, %r8;
setp.ge.s32 %p1, %r1, %r2;
@%p1 bra BB0_2;
cvta.to.global.u64 %rd10, %rd4;
mul.wide.s32 %rd11, %r1, 4;
add.s64 %rd12, %rd10, %rd11;
cvta.to.global.u64 %rd13, %rd5;
add.s64 %rd14, %rd13, %rd11;
cvta.to.global.u64 %rd15, %rd6;
add.s64 %rd16, %rd15, %rd11;
cvta.to.global.u64 %rd17, %rd7;
add.s64 %rd18, %rd17, %rd11;
cvta.to.global.u64 %rd19, %rd8;
add.s64 %rd20, %rd19, %rd11;
cvta.to.global.u64 %rd21, %rd9;
add.s64 %rd22, %rd21, %rd11;
ld.global.f32 %f1, [%rd22];
ld.global.f32 %f2, [%rd14];
mul.f32 %f3, %f2, %f1;
ld.global.f32 %f4, [%rd20];
ld.global.f32 %f5, [%rd16];
mul.f32 %f6, %f5, %f4;
sub.f32 %f7, %f3, %f6;
ld.global.f32 %f8, [%rd18];
mul.f32 %f9, %f5, %f8;
ld.global.f32 %f10, [%rd12];
mul.f32 %f11, %f10, %f1;
sub.f32 %f12, %f9, %f11;
mul.f32 %f13, %f10, %f4;
mul.f32 %f14, %f2, %f8;
sub.f32 %f15, %f13, %f14;
cvta.to.global.u64 %rd23, %rd1;
add.s64 %rd24, %rd23, %rd11;
st.global.f32 [%rd24], %f7;
cvta.to.global.u64 %rd25, %rd2;
add.s64 %rd26, %rd25, %rd11;
st.global.f32 [%rd26], %f12;
cvta.to.global.u64 %rd27, %rd3;
add.s64 %rd28, %rd27, %rd11;
st.global.f32 [%rd28], %f15;
BB0_2:
ret;
}