A platform to build and run apps that are elastic, agile, and resilient. SDK, libraries, and hosted environments.

Chisel: A Modern Hardware Design Language

Rocket Chip Generator

SonicBOOM: The Berkeley Out-of-Order Machine

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Source files for SiFive's Freedom platforms

Flexible Intermediate Representation for RTL

educational microarchitectures for risc-v isa

A template project for beginning new Chisel work

Simple RISC-V 3-stage Pipeline in Chisel

An interactive playground for Scala

An embedded Insane-specific Language for Scala implementing the BASIC programming language

A Library of Chisel3 Tools for Digital Signal Processing

Common RTL blocks used in SiFive's projects

YAML parser for circe using SnakeYAML

Provides various testers for chisel users

This is the example language I demonstrated at JavaOne at my BOF session.

A DMA Controller for RISCV CPUs

JTAG generator in Chisel

split from rocketchip, try to add test and doc to it.

The second iteration of RISCV DMA accelerator