Stackup
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The PCB is designed to be produced with 4 layers using the JLCPCB (https://jlcpcb.com/) JLC2313 stackup. (0.1mm prepreg (eps_r = 4.05) between the outer and inner layer.)

Using the JLCPCB impedance calculator, the following trace parameters were obtained:

100Ω differential:
4.00mil (102µm) trace width / 5.00mil (127µm) space

50Ω single-ended:
5.78mil (147µm) trace width

Ground spacing: 200µm


Vias
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JLC multilayer: min. via drill: 0.2mm, min. via diameter: 0.45 mm