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Commits on May 13, 2017

• controller: Fix precharge bit

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• controller: fix rd_ready bit

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Commits on Apr 26, 2017

• controller: Fix whitespace

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Commits on Feb 3, 2017

• Remove last sdram file

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• Remove unused files

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• Add the generated project files from fusesoc

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Commits on Sep 13, 2016

• fusesoc: convert to filesets and make top and tb stuff private

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Commits on Aug 26, 2016

• fifo/ctrl: Add fixes from digi recorder project

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• readme: add some details on the build

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• testcases: get test cases working

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• toplevel: finish toplevel wiring

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Commits on Aug 25, 2016

• Merge branch 'master' of github.com:stffrdhrn/sdram-controller

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• fusesoc: adding fusesoc build for sdram

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Commits on Jun 22, 2015

• Update diagram to match current implementation

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Commits on Jun 18, 2015

• fix schematic

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• update image

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• add an image of the top schematic

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• status is stable again

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• fix some wiring

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• make sure we define the widths

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• fix a few isues with toplevel

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• wire everything together

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• working on cdc

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Commits on Jun 15, 2015

• Add small test to confirm fifo works

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Commits on Jun 14, 2015

• forgot to use syncrhonized signal

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• working on fifo and moving interface to 1Mhz low freq clock

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Commits on Jun 9, 2015

• Merge branch 'master' of github.com:stffrdhrn/sdram-controller

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• make the controller all register on the posedge (more simple pipelining to sdram)

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Commits on Jun 6, 2015

• forgot one

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• change non-blocking combinational logic to block (cliff cummings)

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Commits on Jun 4, 2015

• fix some typos

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Commits on Jun 3, 2015

• update readme

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• update readme

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• update readme

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Commits on Jun 2, 2015

• add block diagram

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