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4 stars written in SystemVerilog
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AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

SystemVerilog 1,069 257 Updated Oct 8, 2024

Framework providing operating system abstractions and a range of shared networking (RDMA, TCP/IP) and memory services to common modern heterogeneous platforms.

SystemVerilog 212 63 Updated Oct 9, 2024

RecoNIC is a software/hardware shell used to enable network-attached processing within an RDMA-featured SmartNIC for scale-out computing.

SystemVerilog 96 23 Updated Oct 9, 2024

ESnet SmartNIC hardware design repository.

SystemVerilog 40 4 Updated Sep 19, 2024