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Adding support for Scalar Cryptography Extension (Crossbar permutation instructions, Zbkx) #27

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format fixes
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munailwaqar committed Jan 24, 2025
commit 7e872b9fb1c79ab43f812685debbaf9df6a3b98f
2 changes: 2 additions & 0 deletions core/alu.sv
Original file line number Diff line number Diff line change
Expand Up @@ -272,6 +272,7 @@ module alu
if (CVA6Cfg.ZKN && CVA6Cfg.RVB) begin : zkn_gen_block
genvar i, m, n, q;
for (i = 0; i < (CVA6Cfg.XLEN / 8); i++) begin : brev8_xperm8_gen
// Generating xperm8_result by extracting bytes from operand a based on indices from operand b
assign xperm8_result[i << 3 +: 8] = (fu_data_i.operand_b[i << 3 +: 8] < (CVA6Cfg.XLEN / 8)) ? fu_data_i.operand_a[fu_data_i.operand_b[i << 3 +: 8] << 3 +: 8] : 8'b0;
// Generate brev8_reversed by reversing bits within each byte
for (m = 0; m < 8; m++) begin : reverse_bits
Expand All @@ -280,6 +281,7 @@ module alu
end
end
for (q = 0; q < (CVA6Cfg.XLEN / 4); q++) begin : xperm4_gen
// Generating xperm4_result by extracting nibbles from operand a based on indices from operand b
assign xperm4_result[q << 2 +: 4] = (fu_data_i.operand_b[q << 2 +: 4] < (CVA6Cfg.XLEN / 4)) ? fu_data_i.operand_a[{2'b0, fu_data_i.operand_b[q << 2 +: 4]} << 2 +: 4] : 4'b0;
end
// Generate zip and unzip results
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14 changes: 12 additions & 2 deletions core/decoder.sv
Original file line number Diff line number Diff line change
Expand Up @@ -782,8 +782,18 @@ module decoder
if (CVA6Cfg.ZKN) instruction_o.op = ariane_pkg::PACK_H; //packh
else illegal_instr_bm = 1'b1;
end
{7'b001_0100, 3'b100} : if (CVA6Cfg.ZKN) instruction_o.op = ariane_pkg::XPERM8; else illegal_instr_bm = 1'b1; // xperm8
{7'b001_0100, 3'b010} : if (CVA6Cfg.ZKN) instruction_o.op = ariane_pkg::XPERM4; else illegal_instr_bm = 1'b1; // xperm4
{
7'b001_0100, 3'b100
} : begin
if (CVA6Cfg.ZKN) instruction_o.op = ariane_pkg::XPERM8; // xperm8
else illegal_instr_bm = 1'b1;
end
{
7'b001_0100, 3'b010
} : begin
if (CVA6Cfg.ZKN) instruction_o.op = ariane_pkg::XPERM4; // xperm4
else illegal_instr_bm = 1'b1;
end
// Zero Extend Op RV32 encoding
{
7'b000_0100, 3'b100
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2 changes: 1 addition & 1 deletion verif/sim/cva6.py
Original file line number Diff line number Diff line change
Expand Up @@ -899,7 +899,7 @@ def load_config(args, cwd):
args.isa = "rv32imac"
elif base == "cv32a6_imac_sv32":
args.mabi = "ilp32"
args.isa = "rv32imac_zbkb"
args.isa = "rv32imac_zbkb_zbkx"
elif base == "cv32a6_imafc_sv32":
args.mabi = "ilp32f"
args.isa = "rv32imafc"
Expand Down