IFU: mmio wait until last instruction retiring

* add 1 stage for mmio_state before sending request to MMIO bus
* check whether the last fetch packet commit all its intructions (the
result of execution path has been decided)
* avoid speculative execution to MMIO bus

src/main/scala/xiangshan/frontend/Frontend.scala

@@ -118,6 +118,8 @@ class FrontendImp (outer: Frontend) extends LazyModuleImp(outer)
   ftq.io.fromIfu          <> ifu.io.ftqInter.toFtq
   bpu.io.ftq_to_bpu       <> ftq.io.toBpu
   ftq.io.fromBpu          <> bpu.io.bpu_to_ftq
+
+  ftq.io.mmioCommitRead   <> ifu.io.mmioCommitRead
   //IFU-ICache
 
   icache.io.fetch.req <> ftq.io.toICache.req

src/main/scala/xiangshan/frontend/FrontendBundle.scala

@@ -102,6 +102,11 @@ class FtqPrefechBundle(implicit p:Parameters) extends XSBundle {
   val req = DecoupledIO(new PrefetchRequest)
 }
 
+class mmioCommitRead(implicit p: Parameters) extends XSBundle {
+  val mmioFtqPtr = Output(new FtqPtr)
+  val mmioLastCommit = Input(Bool())
+}
+
 class FetchToIBuffer(implicit p: Parameters) extends XSBundle {
   val instrs    = Vec(PredictWidth, UInt(32.W))
   val valid     = UInt(PredictWidth.W)

src/main/scala/xiangshan/frontend/IFU.scala

@@ -55,6 +55,7 @@ class UncacheInterface(implicit p: Parameters) extends XSBundle {
   val fromUncache = Flipped(DecoupledIO(new InsUncacheResp))
   val toUncache   = DecoupledIO( new InsUncacheReq )
 }
+
 class NewIFUIO(implicit p: Parameters) extends XSBundle {
   val ftqInter        = new FtqInterface
   val icacheInter     = Flipped(new IFUICacheIO)
@@ -67,6 +68,7 @@ class NewIFUIO(implicit p: Parameters) extends XSBundle {
   val rob_commits = Flipped(Vec(CommitWidth, Valid(new RobCommitInfo)))
   val iTLBInter       = new TlbRequestIO
   val pmp             =   new ICachePMPBundle
+  val mmioCommitRead  = new mmioCommitRead
 }
 
 // record the situation in which fallThruAddr falls into
@@ -388,8 +390,11 @@ class NewIFU(implicit p: Parameters) extends XSModule
   val mmio_resend_af  = RegInit(false.B)
   val mmio_resend_pf  = RegInit(false.B)
 
+  //last instuction finish
+  val is_first_instr = RegInit(true.B)
+  io.mmioCommitRead.mmioFtqPtr := RegNext(f3_ftq_req.ftqIdx + 1.U)
 
-  val m_idle :: m_sendReq :: m_waitResp :: m_sendTLB :: m_tlbResp :: m_sendPMP :: m_resendReq :: m_waitResendResp :: m_waitCommit :: m_commited :: Nil = Enum(10)
+  val m_idle :: m_waitLastCmt:: m_sendReq :: m_waitResp :: m_sendTLB :: m_tlbResp :: m_sendPMP :: m_resendReq :: m_waitResendResp :: m_waitCommit :: m_commited :: Nil = Enum(11)
   val mmio_state = RegInit(m_idle)
 
   val f3_req_is_mmio     = f3_mmio && f3_valid
@@ -406,6 +411,10 @@ class NewIFU(implicit p: Parameters) extends XSModule
 
   val f3_need_not_flush = f3_req_is_mmio && fromFtqRedirectReg.valid && !f3_ftq_flush_self && !f3_ftq_flush_by_older
 
+  when(is_first_instr && mmio_commit){
+    is_first_instr := false.B
+  }
+
   when(f3_flush && !f3_need_not_flush)               {f3_valid := false.B}
   .elsewhen(f2_fire && !f2_flush )                   {f3_valid := true.B }
   .elsewhen(io.toIbuffer.fire() && !f3_req_is_mmio)          {f3_valid := false.B}
@@ -421,11 +430,19 @@ class NewIFU(implicit p: Parameters) extends XSModule
 
   f3_ready := Mux(f3_req_is_mmio, io.toIbuffer.ready && f3_mmio_req_commit || !f3_valid , io.toIbuffer.ready || !f3_valid)
 
-
+  // mmio state machine
   switch(mmio_state){
     is(m_idle){
       when(f3_req_is_mmio){
-        mmio_state :=  m_sendReq
+        mmio_state :=  m_waitLastCmt
+      }
+    }
+
+    is(m_waitLastCmt){
+      when(is_first_instr){
+        mmio_state := m_sendReq
+      }.otherwise{
+        mmio_state := Mux(io.mmioCommitRead.mmioLastCommit, m_sendReq, m_waitLastCmt)
       }
     }
 
@@ -461,9 +478,9 @@ class NewIFU(implicit p: Parameters) extends XSModule
     }
 
     is(m_sendPMP){
-          val pmpExcpAF = io.pmp.resp.instr || !io.pmp.resp.mmio
-          mmio_state :=  Mux(pmpExcpAF, m_waitCommit , m_resendReq)
-          mmio_resend_af := pmpExcpAF
+      val pmpExcpAF = io.pmp.resp.instr || !io.pmp.resp.mmio
+      mmio_state :=  Mux(pmpExcpAF, m_waitCommit , m_resendReq)
+      mmio_resend_af := pmpExcpAF
     }
 
     is(m_resendReq){
@@ -485,9 +502,9 @@ class NewIFU(implicit p: Parameters) extends XSModule
 
     //normal mmio instruction
     is(m_commited){
-        mmio_state := m_idle
-        mmio_is_RVC := false.B
-        mmio_resend_addr := 0.U
+      mmio_state := m_idle
+      mmio_is_RVC := false.B
+      mmio_resend_addr := 0.U
     }
   }
 

src/main/scala/xiangshan/frontend/NewFtq.scala

@@ -442,6 +442,8 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
       val bpRight = Output(UInt(XLEN.W))
       val bpWrong = Output(UInt(XLEN.W))
     }
+
+    val mmioCommitRead = Flipped(new mmioCommitRead)
   })
   io.bpuInfo := DontCare
 
@@ -1013,6 +1015,11 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
       s === c_invalid || s === c_commited
     })).andR()
 
+  val mmioReadPtr = io.mmioCommitRead.mmioFtqPtr
+  val mmioLastCommit = isBefore(commPtr, mmioReadPtr) && (isAfter(ifuPtr,mmioReadPtr)  ||  mmioReadPtr ===   ifuPtr) &&
+                       Cat(commitStateQueue(mmioReadPtr.value).map(s => { s === c_invalid || s === c_commited})).andR()
+  io.mmioCommitRead.mmioLastCommit := RegNext(mmioLastCommit)
+
   // commit reads
   val commit_pc_bundle = RegNext(ftq_pc_mem.io.commPtr_rdata)
   val commit_target =