<bug-fix> cancel f3_lastHalf_valid (OpenXiangShan#1737)

src/main/scala/xiangshan/frontend/IFU.scala

@@ -550,6 +550,10 @@ class NewIFU(implicit p: Parameters) extends XSModule
   val f3_lastHalf_mask    = VecInit((0 until PredictWidth).map( i => if(i ==0) false.B else true.B )).asUInt()
   val f3_lastHalf_disable = RegInit(false.B)
 
+  when(f3_flush || (f3_fire && f3_lastHalf_disable)){
+    f3_lastHalf_disable := false.B
+  }
+
   when (f3_flush) {
     f3_lastHalf.valid := false.B
   }.elsewhen (f3_fire) {
@@ -678,13 +682,22 @@ class NewIFU(implicit p: Parameters) extends XSModule
   /** if a req with a last half but miss predicted enters in wb stage, and this cycle f3 stalls,  
     * we set a flag to notify f3 that the last half flag need not to be set.
     */
+  //f3_fire is after wb_valid
   when(wb_valid && RegNext(f3_hasLastHalf) 
         && wb_check_result_stage2.fixedMissPred(PredictWidth - 1) 
         && !f3_lastHalf.valid && !f3_fire
       ){
     f3_lastHalf_disable := true.B
   }
 
+  //wb_valid and f3_fire are in same cycle
+  when(wb_valid && RegNext(f3_hasLastHalf) 
+        && wb_check_result_stage2.fixedMissPred(PredictWidth - 1) 
+        && !f3_lastHalf.valid && f3_fire
+      ){
+    f3_lastHalf.valid := false.B
+  }
+
   val checkFlushWb = Wire(Valid(new PredecodeWritebackBundle))
   checkFlushWb.valid                  := wb_valid
   checkFlushWb.bits.pc                := wb_pc