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Commits on Jun 8, 2021

• readme: replace arch diagram

  wakafa1

  committed
  6d529dd

• readme: update readme

  wakafa1

  committed
  40adeb5

Commits on Jun 4, 2021

• CSR: fix mip/sip implementation (OpenXiangShan#823)

  Show description for ab2d190
  AugustusWillisWang

  authored
  ab2d190

• Add MulanPSL-2.0 License (OpenXiangShan#824)

  Show description for c6d4398
  Lemover

  authored
  c6d4398

Commits on Jun 1, 2021

• Connect rtc_tick to clint (OpenXiangShan#822)

  ljwljwljwljw

  authored
  330595d

Commits on May 27, 2021

• backend, rs: support multiple enqueue and dequeue instructions (OpenXiangShan#820)

  Show description for 29a0599
  poemonsense

  authored
  29a0599

Commits on May 25, 2021

• device: add AXI4IntrGenerator to generate external interrupts (OpenXiangShan#819)

  Show description for b6a21a2
  poemonsense

  authored
  b6a21a2

Commits on May 22, 2021

• Update README.md (OpenXiangShan#818)

  poemonsense

  authored
  a2ba9cd

Commits on May 18, 2021

• ifu: when mispredicted inst is br, we should also shift ghr (OpenXiangShan#771)

  Lingrui98

  authored
  bb762f6

• Auto generate dts with diplomacy (OpenXiangShan#817)

  Show description for afcc4f2
  ljwljwljwljw

  authored
  afcc4f2

• PTW: add perf counter for req's count and cycle (OpenXiangShan#814)

  Show description for 6527e46
  Lemover

  authored
  6527e46

Commits on May 17, 2021

• Merge pull request OpenXiangShan#815 from RISCVERS/fix-misleading-cmd

  Show description for 0a1a21a
  sashimi-yzh

  authored
  0a1a21a

• README.md: fix example commands

  sashimi-yzh

  committed
  52ef0d7

Commits on May 15, 2021

• backend,RS: rewrite RS to optimize timing (OpenXiangShan#812)

  Show description for 5c7674f
  poemonsense

  authored
  5c7674f

Commits on May 12, 2021

• PTW: rewrite ptw for multiple requests support (OpenXiangShan#811)

  Show description for 4d586ba
  Lemover

  authored
  4d586ba

• Update mill and rocket-chip (OpenXiangShan#810)

  ljwljwljwljw

  authored
  16cf0dd

• Configs: update MinimalConfig for FPGA (OpenXiangShan#809)

  Show description for 05f23f5
  AugustusWillisWang

  authored
  05f23f5

Commits on May 11, 2021

• test,vcs: call $finish when difftest fails (OpenXiangShan#808)

  poemonsense

  authored
  632fc81

• backend,mem: add Store Sets memory dependence predictor (OpenXiangShan#796)

  Show description for de169c6
  

  AugustusWillisWang

  and

  Lemover

  authored
  de169c6

Commits on May 9, 2021

• vcs,main: exit on assertion and difftest failures (OpenXiangShan#806)

  poemonsense

  authored
  7ebd1b2

• bundle: use Vec for src in ExuInput (OpenXiangShan#805)

  Show description for 2bd5334
  poemonsense

  authored
  2bd5334

Commits on May 7, 2021

• Merge pull request OpenXiangShan#804 from RISCVERS/dev-config

  Show description for ff287d1
  AugustusWillisWang

  authored
  ff287d1

• Disable L2 and L3 in MinimalConfig

  ljwljwljwljw

  committed
  175bcfe

• Rewrite arg parser

  ljwljwljwljw

  committed
  45c767e

• scripts,ci: add simple python wrapper and use it for CI (OpenXiangShan#802)

  Show description for c11a4d2
  

  poemonsense

  and

  AugustusWillisWang

  authored
  c11a4d2

• test: add support for VCS simulation (OpenXiangShan#803)

  Show description for acd0ebb
  poemonsense

  authored
  acd0ebb

Commits on May 6, 2021

• Config: add MinimalConfig

  Show description for ec5c8ac
  AugustusWillisWang

  committed
  ec5c8ac

• Backend: add mul to fast wakeup (OpenXiangShan#769)

  Show description for 22deac3
  Lemover

  authored
  22deac3

Commits on May 5, 2021

• dispatch1: allow enq.ready when !enq.valid (OpenXiangShan#799)

  poemonsense

  authored
  fd13f5e

Commits on May 4, 2021

• DispatchQueue: wrap around tailPtr index when redirect (OpenXiangShan#800)

  Show description for 695364a
  poemonsense

  authored
  695364a

Commits on May 1, 2021

• bundle,uop: use Vec for lsrc, psrc, srcState and srcType (OpenXiangShan#797)

  Show description for 20e31bd
  poemonsense

  authored
  20e31bd

Commits on Apr 30, 2021

• emu: add --force-dump-result option (OpenXiangShan#791)

  Show description for a974979
  AugustusWillisWang

  authored
  a974979

• cache: support fake dcache, ptw, l1pluscache, l2cache and l3cache (OpenXiangShan#795)

  Show description for 9d5a202
  poemonsense

  authored
  9d5a202

• MemBlock: split store addr and store data (OpenXiangShan#781)

  Show description for 1b7aded
  

  AugustusWillisWang

  and

  Lemover

  authored
  1b7aded

Commits on Apr 29, 2021

• difftest: support SMP difftest (OpenXiangShan#786)

  Show description for 68f25d3
  wakafa1

  authored
  68f25d3

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