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Commits on Nov 15, 2022

• Merge pull request OpenXiangShan#1824 from OpenXiangShan/bump-chisel-circt

  Show description for 28ab2f5
  ljwljwljwljw

  authored
  28ab2f5

Commits on Nov 9, 2022

• misc: bump chisel-circt

  ljwljwljwljw

  committed
  714ba5a

Commits on Jul 7, 2022

• Update build.sc (OpenXiangShan#1622)

  Show description for 7861bfd
  ljwljwljwljw

  authored
  7861bfd

Commits on Jun 25, 2022

• Merge pull request OpenXiangShan#1587 from OpenXiangShan/chisel-db

  Show description for b54c2fd
  ljwljwljwljw

  authored
  b54c2fd

Commits on Jun 24, 2022

• Added chisel-db to dump hw data into a database automatically

  ljwljwljwljw

  committed
  a093889

Commits on Apr 1, 2022

• Merge pull request OpenXiangShan#1517 from OpenXiangShan/circt-support

  Show description for 128703a
  ljwljwljwljw

  authored
  128703a

Commits on Mar 31, 2022

• Misc: add support for compiling with CIRCT

  ljwljwljwljw

  committed
  cc35871

• Makefile: also gen time.log when make verilog

  ljwljwljwljw

  committed
  b3b1e5c

• Bump chisel to 3.5.0

  ljwljwljwljw

  committed
  9658ce5

Commits on Mar 26, 2022

• Bump rocket-chip (OpenXiangShan#1502)

  ljwljwljwljw

  authored
  12e221b

Commits on Feb 18, 2022

• Add IDE support into Makefile and README (OpenXiangShan#1470)

  ljwljwljwljw

  authored
  0af3f74

Commits on Feb 8, 2022

• SoC: remove error_xbar; add more buffers (OpenXiangShan#1454)

  Show description for acc8888
  ljwljwljwljw

  authored
  acc8888

Commits on Feb 1, 2022

• Bump huancun (OpenXiangShan#1446)

  ljwljwljwljw

  authored
  6427650

Commits on Jan 28, 2022

• SoC: timing opt (OpenXiangShan#1431)

  Show description for 752db3a
  

  ljwljwljwljw

  and

  poemonsense

  authored
  752db3a

• Adjusted reset signals (OpenXiangShan#1441)

  Show description for 25cb35b
  ljwljwljwljw

  authored
  25cb35b

Commits on Jan 7, 2022

• Connect L2 ecc error to BEU / Connect L3 ecc error to PLIC (OpenXiangShan#1415)

  Show description for 3800524
  ljwljwljwljw

  authored
  3800524

• SoC: Buffer adjustment (OpenXiangShan#1403)

  Show description for b7291c0
  ljwljwljwljw

  authored
  b7291c0

Commits on Dec 17, 2021

• Change default L3 size to 6MB (OpenXiangShan#1365)

  Show description for 0fbed46
  ljwljwljwljw

  authored
  0fbed46

Commits on Dec 13, 2021

• SoC: insert more buffers into mmio path (OpenXiangShan#1329)

  Show description for be340b1
  

  4 peopleauthored
  be340b1

Commits on Dec 12, 2021

• L2/L3: fix prefetch train address (OpenXiangShan#1339)

  Show description for 459ad1b
  ljwljwljwljw

  authored
  459ad1b

Commits on Dec 6, 2021

• DTS: add interrupt-controller into cpu (OpenXiangShan#1298)

  ljwljwljwljw

  authored
  7ba24bb

• Add pma checker for I/O device (OpenXiangShan#1300)

  Show description for 98c7160
  

  3 peopleauthored
  98c7160

Commits on Dec 2, 2021

• Bump fudian (OpenXiangShan#1293)

  ljwljwljwljw

  authored
  1b5e3cd

Commits on Dec 1, 2021

• Change L2 to 4 banks (OpenXiangShan#1256)

  Show description for 59239bc
  ljwljwljwljw

  authored
  59239bc

• Clean up project dependencies (OpenXiangShan#1282)

  Show description for 7206088
  ljwljwljwljw

  authored
  7206088

Commits on Nov 21, 2021

• SoC timing fix (OpenXiangShan#1253)

  Show description for cac098b
  ljwljwljwljw

  authored
  cac098b

Commits on Nov 16, 2021

• Fix multi-core dedup bug (OpenXiangShan#1235)

  Show description for 5668a92
  ljwljwljwljw

  authored
  5668a92

Commits on Nov 9, 2021

• SoC: change buffer latency && set L3 size to 8MB (OpenXiangShan#1205)

  Show description for 29230e8
  ljwljwljwljw

  authored
  29230e8

Commits on Oct 30, 2021

• Refactor config & Add pll (OpenXiangShan#1181)

  Show description for 34ab1ae
  ljwljwljwljw

  authored
  34ab1ae

Commits on Oct 29, 2021

• Add FADD/FMUL pipeline (OpenXiangShan#1186)

  ljwljwljwljw

  authored
  a273862

Commits on Oct 27, 2021

• Optimize L2->L3 crossbar (OpenXiangShan#1177)

  Show description for a9f27ba
  ljwljwljwljw

  authored
  a9f27ba

Commits on Oct 24, 2021

• Config update (OpenXiangShan#1164)

  Show description for 496c0ad
  ljwljwljwljw

  authored
  496c0ad

Commits on Oct 16, 2021

• Update PrintCtrl transform (OpenXiangShan#1122)

  Show description for f79ff60
  ljwljwljwljw

  authored
  f79ff60

Commits on Oct 13, 2021

• Refactor top (OpenXiangShan#1093)

  Show description for 73be64b
  

  ljwljwljwljw

  and

  fwzhang

  authored
  73be64b

Commits on Oct 6, 2021

• Bump huancun (MSHR bug fix) (OpenXiangShan#1088)

  Show description for c41c367
  ljwljwljwljw

  authored
  c41c367

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