DTS: add interrupt-controller into cpu (OpenXiangShan#1298)

src/main/scala/xiangshan/XSDts.scala

@@ -84,7 +84,40 @@ trait HasXSDts {
       Description(name, mapping ++ cpuProperties ++ nextLevelCacheProperty ++ tileProperties)
     }
   }
+
+  val intcDevice = new DeviceSnippet {
+    override def parent = Some(device)
+    def describe(): Description = {
+      Description("interrupt-controller", Map(
+        "compatible"           -> "riscv,cpu-intc".asProperty,
+        "interrupt-controller" -> Nil,
+        "#interrupt-cells"     -> 1.asProperty))
+    }
+  }
+
   ResourceBinding {
     Resource(device, "reg").bind(ResourceAddress(coreParams.HartId))
+    val int_resources = (
+      clint_int_sink.edges.in.flatMap(_.source.sources) ++
+      plic_int_sink.edges.in.flatMap(_.source.sources) ++
+      debug_int_sink.edges.in.flatMap(_.source.sources)
+      ).flatMap {
+      s =>
+        println(s.resources.map(_.key), s.range)
+        (s.range.start until s.range.`end`).map(_ => s.resources)
+    }
+    val int_ids = Seq(
+      3,    // msip  [clint]
+      7,    // mtip  [clint]
+      11,   // meip  [plic]
+      9,    // seip  [plic]
+      65535 // debug [debug]
+    )
+    assert(int_resources.size == int_ids.size)
+    for((resources, id) <- int_resources.zip(int_ids)){
+      for(r <- resources){
+        r.bind(intcDevice, ResourceInt(id))
+      }
+    }
   }
 }

src/test/scala/top/SimTop.scala

@@ -26,6 +26,8 @@ import xiangshan.{DebugOptions, DebugOptionsKey}
 import chipsalliance.rocketchip.config._
 import freechips.rocketchip.devices.debug._
 import difftest._
+import freechips.rocketchip.util.ElaborationArtefacts
+import top.TopMain.writeOutputFile
 
 class SimTop(implicit p: Parameters) extends Module {
   val debugOpts = p(DebugOptionsKey)
@@ -103,5 +105,8 @@ object SimTop extends App {
         DisableMonitors(p => new SimTop()(p))(config)
       })
     ))
+    ElaborationArtefacts.files.foreach{ case (extension, contents) =>
+      writeOutputFile("./build", s"XSTop.${extension}", contents())
+    }
   }
 }