KianV Linux RISC-V Harris Edition (SOC) RISC-V is an open standard instruction set architecture (ISA) based on reduced instruction set computer (RISC) principles. After successfully earning my **HarveyMuddX-ENGR85B** certification, I acquired the skills to design a hierarchical RISC-V CPU.

In the previous year, I completed an exam on Building a RISC-V CPU Core. This experience led me to refine my prior RISC-V SOC, the kianv simple edition. This initial endeavor was a significant learning curve, crafted through trial and error without simulation. It provided invaluable insights into logical design thinking. Review the archived implementation..

Linux SOC

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|  |/  |__|.---.-.-----.|   |   |     |_|__|.-----.--.--.--.--.
|     <|  ||  _  |     ||   |   |       |  ||     |  |  |_   _|
|__|\__|__||___._|__|__| \_____/|_______|__||__|__|_____|__.__|

KianV RISC-V Linux: Booting Linux like never before!

With KianV RISC-V Linux, booting Linux is not just possible, it's exhilarating. That's right! If you've ever wanted to experience Linux booting in a whole new light, this is your chance. 🔗 Dive deep into the implementation details here. 🎥 Or, if you're more of a visual learner, watch the Kian Linux Soc in action!

Some Hardware designs can be found here

Hardware designs