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Linux 内核揭秘

Python 7,297 1,204 Updated Dec 19, 2024

A simple, scalable, source-synchronous, all-digital DDR link

SystemVerilog 22 9 Updated Feb 8, 2025
2 5 Updated Mar 2, 2022

A Very Low-Bitrate Codec for Speech Compression

C++ 3,852 358 Updated Aug 20, 2024

High throughput JPEG decoder in Verilog for FPGA

Verilog 222 43 Updated Mar 5, 2022

MIPI DSI controller

HTML 70 27 Updated Jun 27, 2022

Tools for Verilog HDL development.

Perl 10 8 Updated Jul 22, 2012

This work is based on PYNQ-Z2 development board provided by organizer, and adopts the cooperation scheme of hardware and software to build a DMA based image data cache transmission system. On this …

VHDL 42 9 Updated Feb 17, 2019

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

SystemVerilog 1,238 278 Updated Mar 21, 2025