This is the Analog Devices Inc. Yocto/OpenEmbedded layer

Linux kernel variant from Analog Devices; see README.md for details

AX7020 board is widely used in security monitoring, automotive electronics, machine vision, intelligent manufacturing, video and audio acquisition and processing, medical equipment, instrumentation…

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

HDL libraries and projects

just for 9361 spi read test using pure HDL

最小和算法实现

ccsds ldpc encdoer and decoder.(CCSDS 131.1-O-2)

Design and RTL implementation of an LDPC decoder.

A 32-bit RISC-V core, with LDPC codec model

A data packing technique for QC-LDPC codec RTL min-sum layer decoding architecture

deep learning accelerator for FPGA and RISC-V

xkDLA：XinKai Deep Learning Accelerator (RTL)

Deep Learning Accelerator (Convolution Neural Networks)

This project accelerates CNN computation with the help of FPGA, for more than 50x speed-up compared with CPU.

The Ultra-Low Power RISC-V Core

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated

NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.

RTL, Cmodel, and testbench for NVDLA

PsPIN: A RISC-V in-network accelerator for flexible high-performance low-power packet processing

A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Accelerator

Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions

关于深度学习算法、框架、编译器、加速器的一些理解

eyeriss-chisel3

APB Logic

PicoRV32 - A Size-Optimized RISC-V CPU

BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/