Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

IC design and development should be faster，simpler and more reliable

AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc

AHB-APB Bridge Design - Internship

Verilog AXI stream components for FPGA implementation

This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块：UART接收器、UART发送器、UART转AXI4交互式调试器。

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware