You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size of the systolic array can be changed, now it is 16X16.

Hardware accelerator for convolutional neural networks

CNN-Accelerator based on FPGA developed by verilog HDL.

Design and Implementation of a GEMM Generator Based on Systolic Array

Implemented Systolic-Array that performs GEMM operation.

GEMM function + testbench

The code repo for GEMM verilog