CNN-Accelerator based on FPGA developed by verilog HDL.

Hardware accelerator for convolutional neural networks

You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size of the systolic array can be changed, now it is 16X16.

Outer product Sparse Matrix Matrix Multiplication

Implemented Systolic-Array that performs GEMM operation.

Design and Implementation of a GEMM Generator Based on Systolic Array

The code repo for GEMM verilog

GEMM function + testbench