Error-bounded Lossy Data Compressor (for floating-point/integer datasets)

hardware (ASIC) DEFLATE designed for low-latency page-granularity memory compression and implemented in Chisel

Intel® Performance Counter Monitor (Intel® PCM)

This code is the implementation of the paper "Reversible Data Hiding in Encrypted Images Based on Multi-MSB Prediction and Huffman Coding".

Massively Parallel Huffman Decoding on GPUs

Artifacts of IPDPS '22 paper "Optimizing Huffman Decoding for Error-Bounded Lossy Compression in GPUs"

Python Module for Huffman Encoding and Decoding

An integrated cache and memory access time, cycle time, area, leakage, and dynamic power model

NVSim - A performance, energy and area estimation tool for non-volatile memory (NVM)

免费书籍汇总。　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　…

分享FPGA开发知识、优秀文章、学习网站以及开源项目。本项目收集了github中许多FPGA开源项目。

The purpose of this project is to address the design and implementation of an intelligent traffic light system based on fuzzy logic technology using Python.

An example of partial reconfiguration

End-to-End Object Detection with Transformers

Avnet Board Definition Files

Vivado Partial Reconfiguration Sample Project for PYNQ-Z1

ReRAM implementation on CNN

This is repo to show how to use nested DFX on ZCU102 board

AiLearning：数据分析+机器学习实战+线性代数+PyTorch+NLTK+TF2

A Dynamic Reconfiguration (DFX) Frontend for Xilinx FPGAs

ARTICo³ - Dynamic and Partially Reconfigurable Architecture for Run-Time Adaptive, High Performance Embedded Computing

Local partial reconfiguration demo

Dynamic Partial Reconfiguration for Real Time Systems

Fast and Flexible FPGA development using Hierarchical Partial Reconfiguration (FPT 2022)

FPGA design automation for real-time, dynamic partially reconfigurable application