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1. 32-point-FFT-Verilog-design-based-DIT-butterfly-algorithm 32-point-FFT-Verilog-design-based-DIT-butterfly-algorithm Public

   This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clock domains and time-shared design

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2. OFDM-System-Simulation OFDM-System-Simulation Public

   The purpose of this project is to simulate the OFDM system for different modulation schemes (BPSK, QPSK, 16QAM), without coding, and using (1/3) repetition coding.

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3. Super-heterodyne-Receiver Super-heterodyne-Receiver Public

   The purpose of this project is to simulate the basic components of an analog communication system using MATLAB programming. Specifically, an AM modulator and a corresponding super-heterodyne receiv…

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4. Meeting-Planner-Based-Binary-Search-Tree Meeting-Planner-Based-Binary-Search-Tree Public

   This planner is mainly depending on the binary search trees. This planner supports five main operations: Add a new plan, modify an existing plan, find an existing plan, delete a plan, and print all…

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5. OpenAnalogDesign OpenAnalogDesign Public

   Forked from mabrains/OpenAnalogDesign

   Open Analog Design Environment

   Makefile 1

6. OpenLane OpenLane Public

   Forked from The-OpenROAD-Project/OpenLane

   OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

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