Update and rework endpoints, update testbenches

Amin-Vossoughian · Sep 12, 2016 · 9e8c93e · 9e8c93e
1 parent 46fedf6
commit 9e8c93e
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Showing 10 changed files with 713 additions and 690 deletions.
diff --git a/tb/axis_ep.py b/tb/axis_ep.py
diff --git a/tb/i2c.py b/tb/i2c.py
@@ -25,37 +25,32 @@
 from myhdl import *
 import mmap
 
-try:
-    from queue import Queue
-except ImportError:
-    from Queue import Queue
-
 class I2CMaster(object):
     def __init__(self):
-        self.command_queue = Queue()
-        self.read_data_queue = Queue()
+        self.command_queue = []
+        self.read_data_queue = []
         self.has_logic = False
         self.clk = None
         self.busy = False
 
     def init_read(self, address, length):
-        self.command_queue.put(('r', address, length))
+        self.command_queue.append(('r', address, length))
 
     def init_write(self, address, data):
-        self.command_queue.put(('w', address, data))
+        self.command_queue.append(('w', address, data))
 
     def idle(self):
-        return self.command_queue.empty() and not self.busy
+        return len(self.command_queue) == 0 and not self.busy
 
     def wait(self):
         while not self.idle():
             yield self.clk.posedge
 
     def read_data_ready(self):
-        return not self.read_data_queue.empty()
+        return len(self.read_data_queue) > 0
 
     def get_read_data(self):
-        return self.read_data_queue.get(False)
+        return self.read_data_queue.pop(0)
 
     def read(self, address, length):
         self.init_read(address, length)
@@ -68,16 +63,17 @@ def write(self, address, data):
         yield self.wait()
 
     def create_logic(self,
-                     clk,
-                     rst,
-                     scl_i,
-                     scl_o,
-                     scl_t,
-                     sda_i,
-                     sda_o,
-                     sda_t,
-                     prescale=2,
-                     name=None):
+                clk,
+                rst,
+                scl_i,
+                scl_o,
+                scl_t,
+                sda_i,
+                sda_o,
+                sda_t,
+                prescale=2,
+                name=None
+            ):
 
         if self.has_logic:
             raise Exception("Logic already instantiated!")
@@ -223,8 +219,8 @@ def logic():
                 self.busy = False
 
                 # check for commands
-                if not self.command_queue.empty():
-                    cmd = self.command_queue.get(False)
+                if len(self.command_queue) > 0:
+                    cmd = self.command_queue.pop(0)
                     self.busy = True
 
                     addr = cmd[1]
@@ -264,7 +260,7 @@ def logic():
                         if name is not None:
                             print("[%s] Read data a:0x%02x d:%s" % (name, addr, " ".join(("{:02x}".format(c) for c in bytearray(data)))))
 
-                        self.read_data_queue.put((addr, data))
+                        self.read_data_queue.append((addr, data))
 
                     else:
                         # bad command; ignore it
@@ -293,16 +289,17 @@ def write_mem(self, address, data):
         self.mem.write(data)
 
     def create_logic(self,
-                     scl_i,
-                     scl_o,
-                     scl_t,
-                     sda_i,
-                     sda_o,
-                     sda_t,
-                     abw=2,
-                     address=0x50,
-                     latency=0,
-                     name=None):
+                scl_i,
+                scl_o,
+                scl_t,
+                sda_i,
+                sda_o,
+                sda_t,
+                abw=2,
+                address=0x50,
+                latency=0,
+                name=None
+            ):
 
         if self.has_logic:
             raise Exception("Logic already instantiated!")

diff --git a/tb/test_i2c.py b/tb/test_i2c.py
@@ -63,44 +63,50 @@ def bench():
     # I2C master
     i2c_master_inst = i2c.I2CMaster()
 
-    i2c_master_logic = i2c_master_inst.create_logic(clk,
-                                                    rst,
-                                                    scl_i=m_scl_i,
-                                                    scl_o=m_scl_o,
-                                                    scl_t=m_scl_t,
-                                                    sda_i=m_sda_i,
-                                                    sda_o=m_sda_o,
-                                                    sda_t=m_sda_t,
-                                                    prescale=2,
-                                                    name='master')
+    i2c_master_logic = i2c_master_inst.create_logic(
+        clk,
+        rst,
+        scl_i=m_scl_i,
+        scl_o=m_scl_o,
+        scl_t=m_scl_t,
+        sda_i=m_sda_i,
+        sda_o=m_sda_o,
+        sda_t=m_sda_t,
+        prescale=2,
+        name='master'
+    )
 
     # I2C memory model 1
     i2c_mem_inst1 = i2c.I2CMem(1024)
 
-    i2c_mem_logic1 = i2c_mem_inst1.create_logic(scl_i=s1_scl_i,
-                                                scl_o=s1_scl_o,
-                                                scl_t=s1_scl_t,
-                                                sda_i=s1_sda_i,
-                                                sda_o=s1_sda_o,
-                                                sda_t=s1_sda_t,
-                                                abw=2,
-                                                address=0x50,
-                                                latency=0,
-                                                name='slave1')
+    i2c_mem_logic1 = i2c_mem_inst1.create_logic(
+        scl_i=s1_scl_i,
+        scl_o=s1_scl_o,
+        scl_t=s1_scl_t,
+        sda_i=s1_sda_i,
+        sda_o=s1_sda_o,
+        sda_t=s1_sda_t,
+        abw=2,
+        address=0x50,
+        latency=0,
+        name='slave1'
+    )
 
     # I2C memory model 2
     i2c_mem_inst2 = i2c.I2CMem(1024)
 
-    i2c_mem_logic2 = i2c_mem_inst2.create_logic(scl_i=s2_scl_i,
-                                                scl_o=s2_scl_o,
-                                                scl_t=s2_scl_t,
-                                                sda_i=s2_sda_i,
-                                                sda_o=s2_sda_o,
-                                                sda_t=s2_sda_t,
-                                                abw=2,
-                                                address=0x51,
-                                                latency=1000,
-                                                name='slave2')
+    i2c_mem_logic2 = i2c_mem_inst2.create_logic(
+        scl_i=s2_scl_i,
+        scl_o=s2_scl_o,
+        scl_t=s2_scl_t,
+        sda_i=s2_sda_i,
+        sda_o=s2_sda_o,
+        sda_t=s2_sda_t,
+        abw=2,
+        address=0x51,
+        latency=1000,
+        name='slave2'
+    )
 
     @always_comb
     def bus():