VLSI Physical Design

Design complexity Tools: Cadence Innovus, Synopsys

Introduction to Physical Design Automation

Moore's Law : "Predicted that the number of transistors of the basic components that you can pack inside a single integrated cicuit would be doubling every eighteen months".

Learning Resources

Here are some collection of resources which were referred to:

Youtube Videos:

VLSI Physical Design

Digital VLSI Design (RTL to GDS)

Electronics - Advanced Logic Synthesis

Websites and blogs:

VLSI System Design

ASIC World

Design Flow

Setting block level constraints,which are mainly:

1. Physical Constraints: These constraints depends on the floor-plan, where exactly a particular block is placed on the top level. 1. Size and shape of the block 2. Pin placement within the block

Some of the physical constraints ar listed below:

• Die Area
• Core placement area
• Utilization area
• Aspect Ratio
• Cell Loaction
• Pin Loaction
• Wiring Keepout

2. Timing Constraints: Delays

Floorplanning and Placement

Routing

Static timing Analysis

Signal Integrity and crosstalk issues

Clocking issues and clock tree synthesis

Low power deign issues

Noise analysis and layout compaction

Physical verification and sign-off