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Commits on Oct 29, 2018

• target/mips: Amend MXU ASE overview note

  Show description for 093ade1
  AMarkovic

  committed
  093ade1

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• target/mips: Move MXU_EN check one level higher

  Show description for e5bf8a0
  AMarkovic

  committed
  e5bf8a0

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• target/mips: Add emulation of MXU instructions S32LDD and S32LDDR

  Show description for 4ca8372
  

  Craig Janeczek

  authored and

  AMarkovic

  committed
  4ca8372

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• target/mips: Add emulation of MXU instructions Q8MUL and Q8MULSU

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  Craig Janeczek

  authored and

  AMarkovic

  committed
  a9a4181

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• target/mips: Add emulation of MXU instruction D16MAC

  Show description for e67915b
  

  Craig Janeczek

  authored and

  AMarkovic

  committed
  e67915b

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• target/mips: Add emulation of MXU instruction D16MUL

  Show description for 72c9bcf
  

  Craig Janeczek

  authored and

  AMarkovic

  committed
  72c9bcf

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• target/mips: Add emulation of MXU instruction S8LDD

  Show description for be57bcd
  

  Craig Janeczek

  authored and

  AMarkovic

  committed
  be57bcd

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• target/mips: Move MUL, S32M2I, S32I2M handling out of main MXU switch

  Show description for 87860df
  AMarkovic

  committed
  87860df

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• target/mips: Add emulation of MXU instructions S32I2M and S32M2I

  Show description for 96992d1
  

  Craig Janeczek

  authored and

  AMarkovic

  committed
  96992d1

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• target/mips: Add emulation of non-MXU MULL within MXU decoding engine

  Show description for 11d56f6
  

  Craig Janeczek

  authored and

  AMarkovic

  committed
  11d56f6

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• target/mips: Add bit encoding for MXU operand getting pattern 'optn3'

  Show description for 53f1131
  

  Craig Janeczek

  authored and

  AMarkovic

  committed
  53f1131

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• target/mips: Add bit encoding for MXU operand getting pattern 'optn2'

  Show description for a35723f
  

  Craig Janeczek

  authored and

  AMarkovic

  committed
  a35723f

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• target/mips: Add bit encoding for MXU execute add/sub pattern 'eptn2'

  Show description for 5bb2999
  AMarkovic

  committed
  5bb2999

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• target/mips: Add bit encoding for MXU accumulate add/sub 2-bit pattern 'aptn2'

  Show description for b70bb91
  

  Craig Janeczek

  authored and

  AMarkovic

  committed
  b70bb91

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• target/mips: Add bit encoding for MXU accumulate add/sub 1-bit pattern 'aptn1'

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  AMarkovic

  committed
  d67da33

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• target/mips: Add MXU decoding engine

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  AMarkovic

  committed
  03f4008

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• target/mips: Add and integrate MXU decoding engine placeholder

  Show description for 0a348b9
  AMarkovic

  committed
  0a348b9

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• target/mips: Amend MXU instruction opcodes

  Show description for eab0bdb
  AMarkovic

  committed
  eab0bdb

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• target/mips: Define a bit for MXU in insn_flags

  Show description for a031ac6
  

  Craig Janeczek

  authored and

  AMarkovic

  committed
  a031ac6

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• target/mips: Introduce MXU registers

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  Craig Janeczek

  authored and

  AMarkovic

  committed
  eb5559f

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• target/mips: Add two missing breaks for NM_LLWPE and NM_SCWPE decoder cases

  Show description for 2431a42
  AMarkovic

  committed
  2431a42

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Commits on Oct 25, 2018

• target/mips: Add disassembler support for nanoMIPS

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  AMarkovic

  committed
  89a955e

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• target/mips: Implement emulation of nanoMIPS EVA instructions

  Show description for d046a9e
  

  Dimitrije Nikolic

  authored and

  AMarkovic

  committed
  d046a9e

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• target/mips: Add nanoMIPS CRC32 instruction pool

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  AMarkovic

  committed
  ba1e811

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Commits on Oct 24, 2018

• target/mips: Fix decoding of ALIGN and DALIGN instructions

  Show description for 373ecd3
  AMarkovic

  committed
  373ecd3

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• target/mips: Fix the title of translate.c

  Show description for ab99e0e
  AMarkovic

  committed
  ab99e0e

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• target/mips: Define the R5900 CPU

  Show description for ed4f49b
  

  frno7

  authored and

  AMarkovic

  committed
  ed4f49b

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• target/mips: Make R5900 DMULT[U], DDIV[U], LL[D] and SC[D] user only

  Show description for 9663132
  

  frno7

  authored and

  AMarkovic

  committed
  9663132

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• target/mips: Support R5900 MOVN, MOVZ and PREF instructions from MIPS IV

  Show description for 5601e62
  

  frno7

  authored and

  AMarkovic

  committed
  5601e62

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• target/mips: Support R5900 DIV1 and DIVU1 instructions

  Show description for be9c42c
  

  frno7

  authored and

  AMarkovic

  committed
  be9c42c

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• target/mips: Support R5900 MFLO1, MTLO1, MFHI1 and MTHI1 instructions

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  frno7

  authored and

  AMarkovic

  committed
  8d927f7

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• target/mips: Support R5900 three-operand MULT1 and MULTU1 instructions

  Show description for 06de726
  

  frno7

  authored and

  AMarkovic

  committed
  06de726

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• target/mips: Support R5900 three-operand MULT and MULTU instructions

  Show description for 21e8e8b
  

  frno7

  authored and

  AMarkovic

  committed
  21e8e8b

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• target/mips: Add a placeholder for R5900 MMI3 instruction subclass

  Show description for ec1944f
  

  frno7

  authored and

  AMarkovic

  committed
  ec1944f

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• target/mips: Add a placeholder for R5900 MMI2 instruction subclass

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  frno7

  authored and

  AMarkovic

  committed
  6c1e48d

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