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xk264:AVC/H.264 Video Encoder IP Core (RTL)

Verilog 30 11 Updated Mar 22, 2023

AVS3 encoder which supports AVS3-P2 baseline profile.

C 141 62 Updated Oct 31, 2024

Cheat Sheet

66 34 Updated Aug 23, 2016

Python Productivity for ZYNQ

Jupyter Notebook 2,036 821 Updated Oct 11, 2024

Vitis AI Lab: MNIST classifier

Python 17 5 Updated Aug 11, 2022

This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems using Vivado HLS. Now under 2018.2 version.

VHDL 71 51 Updated Apr 18, 2019

PYNQ Composabe Overlays

Tcl 70 23 Updated Jun 17, 2024
Jupyter Notebook 59 24 Updated Sep 22, 2022

Ethernet Example Projects targeting the Xilinx ZCU102 evaluation board. This repository replaces XAPP1305.

C 58 38 Updated Dec 16, 2024

Vitis In-Depth Tutorials

C 1,306 559 Updated Jan 24, 2025

Bitmap Processing Library & AXI-Stream Video Image VIP

SystemVerilog 30 5 Updated Apr 11, 2022

Deep Laplacian Pyramid Networks for Fast and Accurate Super-Resolution (CVPR 2017)

MATLAB 450 119 Updated Dec 9, 2017