This project aims to build an Embedded Linux System, in order to analyze the chip from the power-on execution of the first instruction to the entire system running, based on qemu simulator developm…

体系结构研讨 + ysyx高阶大纲 (WIP

Unit tests generator for RVV 1.0

RISC-V Opcodes

The Scala parser to parse riscv/riscv-opcodes generate

SystemVerilog linter

👩‍💻 A CLI Tool for Command Line Insights

ripgrep recursively searches directories for a regex pattern while respecting your gitignore

A RISC-V ELF psABI Document

Common SystemVerilog components

Open-source non-blocking L2 cache

SystemVerilog language server

A Hardware Description Language based on the Rust Programming Language

Rocket Chip Generator

Working Draft of the RISC-V Debug Specification Standard

Intel® Implicit SPMD Program Compiler

RTL, Cmodel, and testbench for NVDLA

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RISC-V Processor Trace Specification

A multi cursor plugin for Neovim.

🇫🇷 Oh my tmux! My self-contained, pretty & versatile tmux configuration made with ❤️

Fully featured & enhanced replacement for copilot.vim complete with API for interacting with Github Copilot

Use your Neovim like using Cursor AI IDE!

Nix template for the chisel-based industrial designing flows.

The source code to the Voss II Hardware Verification Suite

Circuit IR Compilers and Tools

A fast Rust JSON library based on SIMD.

YADR - The best vim,git,zsh plugins and the cleanest vimrc you've ever seen

✨ Magical shell history