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@CrevinnTeoranta

CrevinnTeoranta

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  1. ibex ibex Public

    Forked from lowRISC/ibex

    Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

    SystemVerilog 1

  2. opentitan opentitan Public

    Forked from lowRISC/opentitan

    OpenTitan: Open source silicon root of trust

    SystemVerilog

  3. fastvdma fastvdma Public

    Forked from antmicro/fastvdma

    Antmicro's fast, vendor-neutral DMA IP in Chisel

    SystemVerilog

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Showing 3 of 3 repositories
  • fastvdma Public Forked from antmicro/fastvdma

    Antmicro's fast, vendor-neutral DMA IP in Chisel

    CrevinnTeoranta/fastvdma’s past year of commit activity
    SystemVerilog 0 MIT 23 0 0 Updated Feb 19, 2021
  • ibex Public Forked from lowRISC/ibex

    Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

    CrevinnTeoranta/ibex’s past year of commit activity
    SystemVerilog 1 Apache-2.0 563 0 0 Updated Feb 18, 2021
  • opentitan Public Forked from lowRISC/opentitan

    OpenTitan: Open source silicon root of trust

    CrevinnTeoranta/opentitan’s past year of commit activity
    SystemVerilog 0 Apache-2.0 807 0 0 Updated Jan 11, 2021

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