misc: do bug fix (OpenXiangShan#1157)

* bump difftest & huancun
DavidAlphaFox · Oct 22, 2021 · a79fef6 · a79fef6
1 parent 67682d0
commit a79fef6
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Showing 7 changed files with 20 additions and 12 deletions.
diff --git a/difftest b/difftest
diff --git a/huancun b/huancun
diff --git a/scripts/utils/convert.sh b/scripts/utils/convert.sh
@@ -99,6 +99,8 @@ func paramstr(chn, param) {
       $i = sprintf("%016lx", $i);
     }
   }
+  $13 = sprintf("user: %lx", $13);
+  $14 = sprintf("echo: %lx", $14);
 }
 
 1                                   # print every line

diff --git a/src/main/scala/xiangshan/XSTile.scala b/src/main/scala/xiangshan/XSTile.scala
@@ -96,9 +96,9 @@ class XSTile()(implicit p: Parameters) extends LazyModule
   if (coreParams.dcacheParametersOpt.nonEmpty) {
     misc.l1d_logger := core.memBlock.dcache.clientNode
   }
-  misc.busPMU := core.frontend.icache.clientNode
+  misc.busPMU := TLLogger(s"L2_L1I_$hardId", !debugOpts.FPGAPlatform) := core.frontend.icache.clientNode
   if (!coreParams.softPTW) {
-    misc.busPMU := core.ptw.node
+    misc.busPMU := TLLogger(s"L2_PTW_$hardId", !debugOpts.FPGAPlatform) := core.ptw.node
   }
   l2cache match {
     case Some(l2) =>

diff --git a/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala b/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
@@ -277,6 +277,7 @@ object TlbCmd {
   def isExec(a: UInt) = a(1,0)===exec
 
   def isAtom(a: UInt) = a(2)
+  def isAmo(a: UInt) = a===atom_write // NOTE: sc mixed
 }
 
 class TlbStorageIO(nSets: Int, nWays: Int, ports: Int)(implicit p: Parameters) extends MMUIOBaseBundle {

diff --git a/src/main/scala/xiangshan/cache/mmu/MMUConst.scala b/src/main/scala/xiangshan/cache/mmu/MMUConst.scala
@@ -87,7 +87,7 @@ trait HasTlbConst extends HasXSParameter {
 
   val sramSinglePort = true
 
-  val timeOutThreshold = 2000
+  val timeOutThreshold = 5000
 
   def get_idx(vpn: UInt, nSets: Int): UInt = {
     vpn(log2Up(nSets)-1, 0)

diff --git a/src/main/scala/xiangshan/cache/mmu/TLB.scala b/src/main/scala/xiangshan/cache/mmu/TLB.scala
@@ -145,14 +145,19 @@ class TLB(Width: Int, q: TLBParameters)(implicit p: Parameters) extends TlbModul
     pmp(i).bits.size := sizeReg
     pmp(i).bits.cmd := cmdReg
 
-    val update = hit && (!perm.a || !perm.d && TlbCmd.isWrite(cmdReg)) // update A/D through exception
+    val ldUpdate = hit && !perm.a && TlbCmd.isRead(cmdReg) && !TlbCmd.isAmo(cmdReg) // update A/D through exception
+    val stUpdate = hit && (!perm.a || !perm.d) && (TlbCmd.isWrite(cmdReg) || TlbCmd.isAmo(cmdReg)) // update A/D through exception
+    val instrUpdate = hit && !perm.a && TlbCmd.isExec(cmdReg) // update A/D through exception
     val modeCheck = !(mode === ModeU && !perm.u || mode === ModeS && perm.u && (!priv.sum || ifecth))
-    val ldPf = !(modeCheck && (perm.r || priv.mxr && perm.x)) && (TlbCmd.isRead(cmdReg) && true.B /* TODO !isAMO*/)
-    val stPf = !(modeCheck && perm.w) && (TlbCmd.isWrite(cmdReg) || false.B /*TODO isAMO. */)
-    val instrPf = !(modeCheck && perm.x) && TlbCmd.isExec(cmdReg)
-    resp(i).bits.excp.pf.ld := (ldPf || update || pf) && vmEnable && hit && !af
-    resp(i).bits.excp.pf.st := (stPf || update || pf) && vmEnable && hit && !af
-    resp(i).bits.excp.pf.instr := (instrPf || update || pf) && vmEnable && hit && !af
+    val ldPermFail = !(modeCheck && (perm.r || priv.mxr && perm.x))
+    val stPermFail = !(modeCheck && perm.w)
+    val instrPermFail = !(modeCheck && perm.x)
+    val ldPf = (ldPermFail || pf) && (TlbCmd.isRead(cmdReg) && !TlbCmd.isAmo(cmdReg))
+    val stPf = (stPermFail || pf) && (TlbCmd.isWrite(cmdReg) || TlbCmd.isAmo(cmdReg))
+    val instrPf = (instrPermFail || pf) && TlbCmd.isExec(cmdReg)
+    resp(i).bits.excp.pf.ld := (ldPf || ldUpdate) && vmEnable && hit && !af
+    resp(i).bits.excp.pf.st := (stPf || stUpdate) && vmEnable && hit && !af
+    resp(i).bits.excp.pf.instr := (instrPf || instrUpdate) && vmEnable && hit && !af
     // NOTE: pf need && with !af, page fault has higher priority than access fault
     // but ptw may also have access fault, then af happens, the translation is wrong.
     // In this case, pf has lower priority than af
+5 −3		src/test/csrc/difftest/goldenmem.cpp
+6 −2		src/test/csrc/plugin/tllogger/tllogger.cpp
+1 −0		src/main/scala/huancun/BaseMSHR.scala
+7 −0		src/main/scala/huancun/MSHRAlloc.scala
+17 −0		src/main/scala/huancun/Slice.scala
+11 −11		src/main/scala/huancun/noninclusive/MSHR.scala