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  1. dynamatic dynamatic Public

    DHLS (Dynamic High-Level Synthesis) compiler based on MLIR

    C++ 104 25

  2. fpga19-MOMS fpga19-MOMS Public

    VHDL 13 4

  3. fpga23-straight-lsq-interface fpga23-straight-lsq-interface Public

    This repository holds the source code, benchmarks and results of the work presented in the paper entitled "Straight to the Queue: Fast Load-Store Queue Allocation in Dataflow Circuits".

    Verilog 5

  4. FRIDA FRIDA Public

    Scala 5

  5. fpl20-placement fpl20-placement Public

    Python 4 2

  6. fpl19-DynaBurst fpl19-DynaBurst Public

    VHDL 4 4

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Showing 10 of 14 repositories
  • dynamatic Public

    DHLS (Dynamic High-Level Synthesis) compiler based on MLIR

    C++ 104 25 46 (5 issues need help) 26 Updated Apr 7, 2025
  • HardCilk Public
    Verilog 0 GPL-3.0 3 0 0 Updated Mar 25, 2025
  • Python 0 4 0 0 Updated Mar 20, 2025
  • FRIDA Public
    Scala 5 BSD-3-Clause 0 0 0 Updated Feb 27, 2025
  • Polygeist Public Forked from llvm/Polygeist

    C/C++ frontend for MLIR. Also features polyhedral optimizations, parallel optimizations, and more!

    C++ 1 130 0 0 Updated Feb 4, 2024
  • circt Public Forked from llvm/circt

    Circuit IR Compilers and Tools

    C++ 0 348 0 0 Updated Jan 18, 2024
  • fpga24-more-ooo Public

    This repository holds the source code, benchmarks and results of the work presented in the "Survival of the Fastest: Enabling More Out-of-Order Execution in Dataflow Circuits" paper, which allows for new levels of out-of-order execution in dataflow circuits that are not supported by prior work.

    C++ 2 MIT 1 0 0 Updated Jan 6, 2024
  • Python 2 MIT 0 0 0 Updated Jan 2, 2023
  • fpga23-straight-lsq-interface Public

    This repository holds the source code, benchmarks and results of the work presented in the paper entitled "Straight to the Queue: Fast Load-Store Queue Allocation in Dataflow Circuits".

    Verilog 5 MIT 0 0 0 Updated Dec 8, 2022
  • Python 3 MIT 2 0 0 Updated Aug 23, 2021

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