Tags: ElectrikSpace/gcc
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Disable TSVC tests on kvx Summary: Those tests timeout on ISS in CI, disable them. gcc/testsuite/ChangeLog: 2023-05-09 Paul Iannetta <[email protected]> * gcc.dg/vect/vect.exp: Disable TSVC tests. Test Plan: CI Reviewers: jvillette, O11 gcc Reviewed By: jvillette, O11 gcc Differential Revision: https://phab.kalray.eu/D28985
Disable TSVC tests on kvx Summary: Those tests timeout on ISS in CI, disable them. gcc/testsuite/ChangeLog: 2023-05-09 Paul Iannetta <[email protected]> * gcc.dg/vect/vect.exp: Disable TSVC tests. Test Plan: CI Reviewers: jvillette, O11 gcc Reviewed By: jvillette, O11 gcc Differential Revision: https://phab.kalray.eu/D28985
Revert "If-convert if-then-else with conditional loads and stores in … …ce3." Summary: This reverts commit a2ab68f. This commit does not traverse linux, revert until stabilization. Test Plan: CI Reviewers: bddinechin, O11 gcc Reviewed By: bddinechin, O11 gcc Differential Revision: https://phab.kalray.eu/D26388
libgomp: cos: use write fence macro for mutex and sem Summary: libgomp: cos: use write fence macro for mutex and sem. libgomp/config/cos/ * mutex.h: use write fence macro for unlock. * bar.h: use write fence macro for post/wait. Test Plan: CI Reviewers: O11 gcc! Differential Revision: https://phab.kalray.eu/D24104
Refactor FP division routines by O. Desrentes. Summary: Add implementations of `__divsf3_RN`, `__divsf3_RU`, `__divsf3_RD`, `__divsf3_RZ`. `__divdf3_RN`, `__divdf3_RU`, `__divdf3_RD`, `__divdf3_RZ` form O. Desrentes. Add top-level dispatch functions `__divsf3` and `__divdf3`. libgcc/ * config.host: change the inclusion order of the makefile fragements so that our comes last and properly overrides previous one. libgcc/config/kvx/ * divdf3.c: refactor code by O. Desrentes; add top-level __divdf3. * divsf3.c: refactor code by O. Desrentes; add top-level __divsf3. * divxf_epilogue: factor out common part. * divxf.h: include file for use by divdf.c and divsf.c. * t-kvx: enable replacement of libgcc __divsf3 and __divdf3. ref D20931 ref T16004 Test Plan: CI Reviewers: bddinechin, O11 gcc! Subscribers: jvillette Maniphest Tasks: T16004 Differential Revision: https://phab.kalray.eu/D21008
Refactor FP division routines by O. Desrentes. Summary: Add implementations of `__divsf3_RN`, `__divsf3_RU`, `__divsf3_RD`, `__divsf3_RZ`. `__divdf3_RN`, `__divdf3_RU`, `__divdf3_RD`, `__divdf3_RZ` form O. Desrentes. Add top-level dispatch functions `__divsf3` and `__divdf3`. libgcc/ * config.host: change the inclusion order of the makefile fragements so that our comes last and properly overrides previous one. libgcc/config/kvx/ * divdf3.c: refactor code by O. Desrentes; add top-level __divdf3. * divsf3.c: refactor code by O. Desrentes; add top-level __divsf3. * divxf_epilogue: factor out common part. * divxf.h: include file for use by divdf.c and divsf.c. * t-kvx: enable replacement of libgcc __divsf3 and __divdf3. ref D20931 ref T16004 Test Plan: CI Reviewers: bddinechin, O11 gcc! Subscribers: jvillette Maniphest Tasks: T16004 Differential Revision: https://phab.kalray.eu/D21008
gcc.target: split architecture-dependent tests Summary: Split a test since the assembly generated by those two builtins differ between the two architectures gcc/testsuite/gcc.target/kvx/ * builtin-alclrd.c: Remove. * builtin-alclrw.c: Remove. * builtin-alclrd-kv3v1.c: New. * builtin-alclrw-kv3v1.c: New. * builtin-alclrd-kv3v2.c: New. * builtin-alclrw-kv3v2.c: New. ref. D21487 Test Plan: CI Reviewers: jvillette, O11 gcc! Differential Revision: https://phab.kalray.eu/D21786
ira-color.c (update_costs_from_allocno): Call ira_init_register_move_… …cost_if_necessary. * ira-color.c (update_costs_from_allocno): Call ira_init_register_move_cost_if_necessary. From-SVN: r276587 (cherry picked from commit 6685c83)
Add builtins for conditional load/store instructions. Summary: Access to memory-mapped registers is best performed through cache-bypass loads with volatile semantics. Exposing the conditional memory accesses for such uses cases is useful in particular for manually pipelined code. Also revise the coprocessor move/load/store/swap implementations. gcc/config/kvx: * builtin.md: add patterns for LOADBZ, LOADHZ, LOADWZ, LOADD, LOADQ, LOADCBZ, LOADCHZ, LOADCWZ, LOADCD, LOADCQ, STOREB, STOREH, STOREW, STORED, STOREQ, STORECB, STORECH, STORECW, STORECD, STORECQ; revise patterns for LOADC64, LOADC128, LOADC256. * extension.md: revise patterns for XLOAD256Q, XLOADC256, XSWAP256. * kv3-registers.h: remove "ERROR" entries in KV3_PGR_REGISTER_NAMES, * kv3-registers.md: added enumeration of coprocessor register names. KV3_QGR_REGISTER_NAMES, KV3_XBR_REGISTER_NAMES, KV3_XVR_REGISTER_NAMES, KV3_XWR_REGISTER_NAMES, KV3_XMR_REGISTER_NAMES. * kvx-builtins.c: add builtins LOADBZ, LOADHZ, LOADWZ, LOADD, LOADQ, LOADCBZ, LOADCHZ, LOADCWZ, LOADCD, LOADCQ, STOREB, STOREH, STOREW, STORED, STOREQ, STORECB, STORECH, STORECW, STORECD, STORECQ. * kvx.c: factor access to multi-register classes in functions (kvx_pgr_reg_name), (kvx_qgr_reg_name), (kvx_xvr_reg_name), (kvx_xwr_reg_name), (kvx_xmr_reg_name); uses thes functions in (kvx_print_operand) and (kvx_regname). * unspec.md: add entries for scalar conditional load/store builtins. gcc/testsuite/gcc.target/kvx/ * scalar_int128.c: regenerate for LOADQ, LOADCQ, STOREQ, STORECQ. * scalar_int32.c: regenerate for LOADWZ, LOADCWZ, STOREW, STORECW. * scalar_int64.c: regenerate for LOADD, LOADCD, STORED, STORECD. * vector_float16x16.c: regenerate for XLOADC256. * vector_float32x8.c: regenerate for XLOADC256. * vector_float64x4.c: regenerate for XLOADC256. * vector_int16x16.c: regenerate for XLOADC256. * vector_int32x8.c: regenerate for XLOADC256. * vector_int64x4.c: regenerate for XLOADC256. * vector_int8x32.c: regenerate for XLOADC256. Test Plan: CI Reviewers: jhascoet, O11 gcc! Differential Revision: https://phab.kalray.eu/D17861
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