opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

PicoRV32 - A Size-Optimized RISC-V CPU

一款专注于Ai翻译的工具，可以用来一键自动翻译RPG SLG游戏，Epub Word TXT小说，Srt Vtt Lrc字幕等等。

Blue topaz themes example vault for Obsidian

A blue theme for Obsidian.

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

SystemVerilog support in VS Code

All in one vscode plugin for HDL development

Open source FPGA-based NIC and platform for in-network compute

Verilog Ethernet components for FPGA implementation

Verilog AXI components for FPGA implementation

RTL, Cmodel, and testbench for NVDLA

An Ethernet MAC conforming to IEEE 802.3

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

Verilog Configurable Cache

Python interface to PCIE

NVIDIA® TensorRT™ is an SDK for high-performance deep learning inference on NVIDIA GPUs. This repository contains the open source components of TensorRT.

🍒 Cherry Studio is a desktop client that supports for multiple LLM providers. Support deepseek-r1

计组CPU实验代码

A maintained ctags implementation

A graphical processor simulator and assembly editor for the RISC-V ISA

RARS -- RISC-V Assembler and Runtime Simulator

Notes of my ZJU courses

32-bit Superscalar RISC-V CPU

RISC-V CPU Core (RV32IM)

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM, 8-bit AVR and 32-bit RISC-V architectures.

LicheeTang 蜂鸟E203 Core