hub: Add option to register wishbone bus

Add an option to register the wishbone busses post-mux. This can help achieve timing, since the phys are often in different parts of the FPGA. Signed-off-by: Sean Anderson <[email protected]>
Forty-Bot · Mar 7, 2023 · cd5a4b2 · cd5a4b2
1 parent 9ea09f5
commit cd5a4b2
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Showing 2 changed files with 51 additions and 12 deletions.
diff --git a/rtl/hub.v b/rtl/hub.v
@@ -14,6 +14,7 @@ module hub (
 	output [PORT_COUNT - 1:0] request_data,
 
 	/* Wishbone management */
+	input wb_rst,
 	output wb_ack, wb_err,
 	input wb_cyc, wb_stb, wb_we,
 	input [PORT_COUNT + 5 - 1:0] wb_addr,
@@ -27,6 +28,7 @@ module hub (
 );
 
 	parameter WISHBONE		= 1;
+	parameter REGISTER_WB		= 1;
 	parameter PORT_COUNT		= 4;
 	parameter ELASTIC_BUF_SIZE	= 5;
 	parameter ENABLE_COUNTERS	= 1;
@@ -91,8 +93,45 @@ module hub (
 	end endgenerate
 
 	genvar i;
-
 	generate for (i = 0; i < PORT_COUNT; i = i + 1) begin : port
+		wire reg_ack, reg_err, reg_cyc, reg_stb, reg_we;
+		wire [4:0] reg_addr;
+		wire [15:0] reg_data_write, reg_data_read;
+
+		if (REGISTER_WB) begin
+			wb_reg #(
+				.ADDR_WIDTH(5)
+			) wb_reg (
+				.clk(clk_125),
+				.rst(wb_rst),
+				.s_ack(bus_ack[i]),
+				.s_err(bus_err[i]),
+				.s_cyc(bus_cyc[i]),
+				.s_stb(bus_stb[i]),
+				.s_we(bus_we[i]),
+				.s_addr(bus_addr[i * 5 +: 5]),
+				.s_data_write(bus_data_write[i * 16 +: 16]),
+				.s_data_read(bus_data_read[i * 16 +: 16]),
+				.m_cyc(reg_cyc),
+				.m_stb(reg_stb),
+				.m_ack(reg_ack),
+				.m_err(reg_err),
+				.m_we(reg_we),
+				.m_addr(reg_addr),
+				.m_data_write(reg_data_write),
+				.m_data_read(reg_data_read)
+			);
+		end else begin
+			assign bus_ack[i] = reg_ack;
+			assign bus_err[i] = reg_err;
+			assign reg_cyc = bus_cyc[i];
+			assign reg_stb = bus_stb[i];
+			assign reg_we = bus_we[i];
+			assign reg_addr = bus_addr[i * 5 +: 5];
+			assign reg_data_write = bus_data_write[i * 16 +: 16];
+			assign bus_data_read[i * 16 +: 16] = reg_data_read;
+		end
+
 		phy_internal #(
 			.WISHBONE(WISHBONE),
 			.ENABLE_COUNTERS(ENABLE_COUNTERS),
@@ -114,14 +153,14 @@ module hub (
 			.mii_rx_dv(rx_dv[i]),
 			.mii_rx_er(rx_er[i]),
 			.mii_rxd(rxd[i * 4 +: 4]),
-			.wb_ack(bus_ack[i]),
-			.wb_err(bus_err[i]),
-			.wb_cyc(bus_cyc[i]),
-			.wb_stb(bus_stb[i]),
-			.wb_we(bus_we[i]),
-			.wb_addr(bus_addr[i * 5 +: 5]),
-			.wb_data_write(bus_data_write[i * 16 +: 16]),
-			.wb_data_read(bus_data_read[i * 16 +: 16]),
+			.wb_ack(reg_ack),
+			.wb_err(reg_err),
+			.wb_cyc(reg_cyc),
+			.wb_stb(reg_stb),
+			.wb_we(reg_we),
+			.wb_addr(reg_addr),
+			.wb_data_write(reg_data_write),
+			.wb_data_read(reg_data_read),
 			.link_status(link_status[i]),
 			.receiving(receiving[i])
 		);

diff --git a/tb/hub.py b/tb/hub.py
@@ -43,7 +43,7 @@ async def test_hub(hub):
 
     # Enable fast link stabilization for testing
     for i in range(4):
-        await wb_xfer(wb, BIT(i + 5) + VCR, VCR_LTEST)
+        await wb_xfer(wb, BIT(i + 5) + VCR, VCR_LTEST, delay=2)
 
     packet = list(as_nibbles((0x55, *b"Hello world!")))
     packet_bits = list(itertools.chain.from_iterable(frame(packet)))
@@ -97,5 +97,5 @@ async def bits():
     await Combine(*(Join(t) for t in receivers))
 
     for i in range(4):
-        assert not await wb_xfer(wb, BIT(i + 5) + BMSR) & BMSR_LSTATUS
-        assert await wb_xfer(wb, BIT(i + 5) + BMSR) & BMSR_LSTATUS
+        assert not await wb_xfer(wb, BIT(i + 5) + BMSR, delay=2) & BMSR_LSTATUS
+        assert await wb_xfer(wb, BIT(i + 5) + BMSR, delay=2) & BMSR_LSTATUS