Unofficial guide for ysyx students applying to ShanghaiTech University

Cheerp - a C/C++ compiler for Web applications - compiles to WebAssembly and JavaScript

十分钟魔法练习

《Learn LLVM 17》的非专业个人翻译

ysyx 开源项目管理委员会

⭐ Canicula OS - 天狼星 OS 一个以好玩为主的（x86-64 / AArch64 / RISC-V64GC）操作系统 A fun-focused (x86-64 / AArch64 / RISC-V64GC) operating system.

3-stage RV32IMACZb* processor with debug

write xiangshan nanhu from scratch

A Primer on Memory Consistency and Cache Coherence (Second Edition) 翻译计划

Vim mode for VSCode, powered by Neovim

GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.

🤖 Just a command runner

SUSTech CS202 (Computer Organization) Project, with CPU hardware implemented in Chisel(Scala) and software cross-compiled from Rust.

Simple MDoc runner for mill

Introduction to Computer Systems (II), Spring 2021

Reverse engineering project focus on Synaptics 06cb:0078 usb fingerprint sensor.

How to make undergraduates or new graduates ready for advanced computer architecture research or modern CPU design

🌳 A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.

函数式编程指南中文版

Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

💥 Highly experimental plugin that completely replaces the UI for messages, cmdline and the popupmenu.

华科毕业论文（本科）的 typst 模板

Test the interception/filter of UDP 53 of your local networks or hotspots.

Source Code for Machine Learning in Action for Python 3.X

host your own cloud for the remarkable

Build your personal knowledge base with Trilium Notes