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  • Peking University
  • Beijing

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5 stars written in SystemVerilog
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chipsalliance / Cores-VeeR-EH1

VeeR EH1 core

SystemVerilog 843 223 Updated May 29, 2023

dumpo / my_verilog_projects

数字IC秋招项目、手撕代码

SystemVerilog 34 5 Updated Apr 22, 2024

KafCoppelia / uvm-mcdf

Mirror of william_william/uvm-mcdf on Gitee

SystemVerilog 20 1 Updated Nov 30, 2022

KafCoppelia / uvm-mcdf_v2

Mirror of william_william/uvm-mcdf_v2 on Gitee

SystemVerilog 8 Updated Nov 30, 2022

huangxc6 / SPI_MS

Final Project - Fa23 (a “SPI_MS Chip” that allows full-duplex, synchronous, serial communication between the Chip and peripherals.)

SystemVerilog 4 Updated Jan 4, 2024