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我的电视 电视直播软件,安装即可使用

C 31,675 3,547 Updated Jun 20, 2024
Python 24 1 Updated Dec 23, 2024

Verilog AXI components for FPGA implementation

Verilog 1,599 468 Updated Dec 7, 2023

Open-source high-performance RISC-V processor

Scala 6,050 733 Updated Feb 8, 2025

VeeR EH1 core

SystemVerilog 843 223 Updated May 29, 2023

cocotb: Python-based chip verification

Python 1,878 534 Updated Feb 7, 2025

verilog practice and learning

Verilog 4 1 Updated Sep 28, 2023

RISC-V Instruction Set Manual

TeX 3,855 667 Updated Feb 6, 2025
Jupyter Notebook 39 4 Updated Jul 16, 2024

Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.

VHDL 12 Updated May 7, 2024

Convolutional accelerator kernel, target ASIC & FPGA

Verilog 178 29 Updated Apr 10, 2023

Template for project1 TPU

Verilog 13 21 Updated May 1, 2021

Hardware and software collaborative design labs and project in the spring semester of 2024

Verilog 2 Updated May 7, 2024
JavaScript 996 157 Updated Nov 29, 2024

We run the E203 based on Genesys2 ,and add some additional IP to develop a powerful system

Verilog 7 2 Updated Feb 20, 2023

Toolchain of PAICORE.

Python 10 4 Updated Feb 3, 2025

免费书籍汇总。                                                                                                                                                                                              …

11,227 1,181 Updated Nov 11, 2024

北京大学软件与微电子学院硕士生课程知识点、作业等汇总【Summary of Knowledge Points and Assignments of Peking University Integrated Circuit Major Courses】

147 20 Updated Apr 19, 2022

A Library for Differentiable Logic Gate Networks

Python 618 58 Updated Mar 19, 2024

提取微信聊天记录,将其导出成HTML、Word、Excel文档永久保存,对聊天记录进行分析生成年度聊天报告,用聊天数据训练专属于个人的AI聊天助手

Python 36,989 3,819 Updated Jan 2, 2025

人人都能用英语

TypeScript 25,777 3,837 Updated Jan 18, 2025

A list of ICs and IPs for AI, Machine Learning and Deep Learning.

PHP 1,657 276 Updated Jun 5, 2024

Final Project - Fa23 (a “SPI_MS Chip” that allows full-duplex, synchronous, serial communication between the Chip and peripherals.)

SystemVerilog 4 Updated Jan 4, 2024
Verilog 15 5 Updated Jun 19, 2021

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

Verilog 2,660 1,025 Updated Mar 24, 2021

The Ultra-Low Power RISC-V Core

Verilog 1,385 352 Updated Oct 9, 2024

Collect important papers about snn

31 7 Updated Jul 15, 2021

北京大学数字集成电路设计课程作业—FPGA设计【Assignment of digital integrated circuit design course of Peking University】

Verilog 30 4 Updated Jan 1, 2022

数字IC相关资料

1,054 302 Updated Nov 17, 2020

Rocket Chip Generator

Scala 3,338 1,148 Updated Jan 30, 2025
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