Topics in Machine Learning Accelerator Design

[TVLSI'23] This repository contains the source code for the paper "FireFly: A High-Throughput Hardware Accelerator for Spiking Neural Networks with Efficient DSP and Memory Optimization"

中国科学院大学(UCAS)2020年春季学期计算机组成原理实验课作业

Labs to learn SpinalHDL

第四届全国大学生嵌入式比赛SoC

Highly configurable out-of-order MIPS32 processor, capable of booting Linux.

DreamCore-docs

xv6-riscv-book中译版

Demo Sources for Learning Spinal HDL

L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC

DeepLearning Basics

16 x 16 bits Signed Interger Number Wallance Multiplier Based on Booth Algorithm

Verilog AXI components for FPGA implementation

A FPGA friendly 32 bit RISC-V CPU implementation

国科大高等数字集成电路分析与设计课程2022fall

This repository is used to release the Labs of Computer Architecture Course from USTC

This repository belongs to UltraMIPS_NSCSCC, and consists of the development of pipeline Cache(ICache/DCache) and associated components for dual-issue cpu.

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

AXI协议规范中文翻译版

UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.

Verilog Configurable Cache

Verilog Cache-4Ways IP development

RISC-V CPU Core (RV32IM)

A template project for beginning new Chisel work

syn script for DC Compiler