Diagrams for visualizing neural network architecture (Created with diagrams.net)

Pytorch implementation of BiFSMNv2, TNNLS 2023

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated

FireSim-NVDLA: NVIDIA Deep Learning Accelerator (NVDLA) Integrated with RISC-V Rocket Chip SoC Running on the Amazon FPGA Cloud

This is originally a collection of papers on neural network accelerators. Now it's more like my selection of research on deep learning and computer architecture.

一个开源的FPGA神经网络加速器。

List of awesome open source hardware tools, generators, and reusable designs

Tengine is a lite, high performance, modular inference engine for embedded device

Run LeNet-5 baremetal

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Common SystemVerilog components

An open source, parameterized SystemVerilog digital hardware IP library

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

Verilog library for ASIC and FPGA designers

FuseSoC standard core library

hardware design of universal NPU(CNN accelerator) for various convolution neural network

Berkeley's Spatial Array Generator

处理器相关文集

Implementation of an NPU that can be integrated into a RISC- V core through X-Interface.

Vector Acceleration IP core for RISC-V*

Microarchitecture implementation of the decoupled vector-fetch accelerator

RISC-V Zve32x Vector Coprocessor

PicoRV32 - A Size-Optimized RISC-V CPU

A higher-level Neural Network library for microcontrollers.

AZPR cpu.《CPU自制入门》附录的Verilog代码，其中的日文注释翻译成了中文。

muRISCV-NN is a collection of efficient deep learning kernels for embedded platforms and microcontrollers.

This repository is a lightweight runtime for RISC-V utility.