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Merge branch 'cxgb4-next'
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Hariprasad Shenai says:

====================
cxgb4/cxgb4vf: Adds support for Chelsio T6 adapter

This patch series adds the following:
Adds NIC driver support for T6 adapter
Adds vNIC driver support for T6 adapter

This patch series has been created against net-next tree and includes
patches on cxgb4 and cxgb4vf driver.

We have included all the maintainers of respective drivers. Kindly review
the change and let us know in case of any review comments.

Thanks

V2:
 Fixed compilation issue, when CHELSIO_T4_FCOE is set
====================

Signed-off-by: David S. Miller <[email protected]>
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@davem330
davem330 committed Jun 2, 2015
2 parents d895112 + 41fc2e4 commit db3397b
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Showing 13 changed files with 932 additions and 172 deletions.
21 changes: 20 additions & 1 deletion drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -224,7 +224,6 @@ struct sge_params {
};

struct tp_params {
unsigned int ntxchan; /* # of Tx channels */
unsigned int tre; /* log2 of core clocks per TP tick */
unsigned int la_mask; /* what events are recorded by TP LA */
unsigned short tx_modq_map; /* TX modulation scheduler queue to */
Expand Down Expand Up @@ -273,6 +272,7 @@ struct pci_params {

#define CHELSIO_T4 0x4
#define CHELSIO_T5 0x5
#define CHELSIO_T6 0x6

enum chip_type {
T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1),
Expand All @@ -284,6 +284,10 @@ enum chip_type {
T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1),
T5_FIRST_REV = T5_A0,
T5_LAST_REV = T5_A1,

T6_A0 = CHELSIO_CHIP_CODE(CHELSIO_T6, 0),
T6_FIRST_REV = T6_A0,
T6_LAST_REV = T6_A0,
};

struct devlog_params {
Expand All @@ -292,6 +296,15 @@ struct devlog_params {
u32 size; /* size of log */
};

/* Stores chip specific parameters */
struct arch_specific_params {
u8 nchan;
u16 mps_rplc_size;
u16 vfcount;
u32 sge_fl_db;
u16 mps_tcam_size;
};

struct adapter_params {
struct sge_params sge;
struct tp_params tp;
Expand All @@ -317,6 +330,7 @@ struct adapter_params {
unsigned char nports; /* # of ethernet ports */
unsigned char portvec;
enum chip_type chip; /* chip code */
struct arch_specific_params arch; /* chip specific params */
unsigned char offload;

unsigned char bypass;
Expand Down Expand Up @@ -850,6 +864,11 @@ enum {
VLAN_REWRITE
};

static inline int is_t6(enum chip_type chip)
{
return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6;
}

static inline int is_t5(enum chip_type chip)
{
return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5;
Expand Down
180 changes: 135 additions & 45 deletions drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1084,72 +1084,159 @@ static inline void tcamxy2valmask(u64 x, u64 y, u8 *addr, u64 *mask)

static int mps_tcam_show(struct seq_file *seq, void *v)
{
if (v == SEQ_START_TOKEN)
seq_puts(seq, "Idx Ethernet address Mask Vld Ports PF"
" VF Replication "
"P0 P1 P2 P3 ML\n");
else {
struct adapter *adap = seq->private;
unsigned int chip_ver = CHELSIO_CHIP_VERSION(adap->params.chip);

if (v == SEQ_START_TOKEN) {
if (adap->params.arch.mps_rplc_size > 128)
seq_puts(seq, "Idx Ethernet address Mask "
"Vld Ports PF VF "
"Replication "
" P0 P1 P2 P3 ML\n");
else
seq_puts(seq, "Idx Ethernet address Mask "
"Vld Ports PF VF Replication"
" P0 P1 P2 P3 ML\n");
} else {
u64 mask;
u8 addr[ETH_ALEN];
struct adapter *adap = seq->private;
bool replicate;
unsigned int idx = (uintptr_t)v - 2;
u64 tcamy = t4_read_reg64(adap, MPS_CLS_TCAM_Y_L(idx));
u64 tcamx = t4_read_reg64(adap, MPS_CLS_TCAM_X_L(idx));
u32 cls_lo = t4_read_reg(adap, MPS_CLS_SRAM_L(idx));
u32 cls_hi = t4_read_reg(adap, MPS_CLS_SRAM_H(idx));
u32 rplc[4] = {0, 0, 0, 0};
u64 tcamy, tcamx, val;
u32 cls_lo, cls_hi, ctl;
u32 rplc[8] = {0};

if (chip_ver > CHELSIO_T5) {
/* CtlCmdType - 0: Read, 1: Write
* CtlTcamSel - 0: TCAM0, 1: TCAM1
* CtlXYBitSel- 0: Y bit, 1: X bit
*/

/* Read tcamy */
ctl = CTLCMDTYPE_V(0) | CTLXYBITSEL_V(0);
if (idx < 256)
ctl |= CTLTCAMINDEX_V(idx) | CTLTCAMSEL_V(0);
else
ctl |= CTLTCAMINDEX_V(idx - 256) |
CTLTCAMSEL_V(1);
t4_write_reg(adap, MPS_CLS_TCAM_DATA2_CTL_A, ctl);
val = t4_read_reg(adap, MPS_CLS_TCAM_DATA1_A);
tcamy = DMACH_G(val) << 32;
tcamy |= t4_read_reg(adap, MPS_CLS_TCAM_DATA0_A);

/* Read tcamx. Change the control param */
ctl |= CTLXYBITSEL_V(1);
t4_write_reg(adap, MPS_CLS_TCAM_DATA2_CTL_A, ctl);
val = t4_read_reg(adap, MPS_CLS_TCAM_DATA1_A);
tcamx = DMACH_G(val) << 32;
tcamx |= t4_read_reg(adap, MPS_CLS_TCAM_DATA0_A);
} else {
tcamy = t4_read_reg64(adap, MPS_CLS_TCAM_Y_L(idx));
tcamx = t4_read_reg64(adap, MPS_CLS_TCAM_X_L(idx));
}

cls_lo = t4_read_reg(adap, MPS_CLS_SRAM_L(idx));
cls_hi = t4_read_reg(adap, MPS_CLS_SRAM_H(idx));

if (tcamx & tcamy) {
seq_printf(seq, "%3u -\n", idx);
goto out;
}

if (cls_lo & REPLICATE_F) {
rplc[0] = rplc[1] = rplc[2] = rplc[3] = 0;
if (chip_ver > CHELSIO_T5)
replicate = (cls_lo & T6_REPLICATE_F);
else
replicate = (cls_lo & REPLICATE_F);

if (replicate) {
struct fw_ldst_cmd ldst_cmd;
int ret;
struct fw_ldst_mps_rplc mps_rplc;
u32 ldst_addrspc;

memset(&ldst_cmd, 0, sizeof(ldst_cmd));
ldst_addrspc =
FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MPS);
ldst_cmd.op_to_addrspace =
htonl(FW_CMD_OP_V(FW_LDST_CMD) |
FW_CMD_REQUEST_F |
FW_CMD_READ_F |
FW_LDST_CMD_ADDRSPACE_V(
FW_LDST_ADDRSPC_MPS));
ldst_addrspc);
ldst_cmd.cycles_to_len16 = htonl(FW_LEN16(ldst_cmd));
ldst_cmd.u.mps.fid_ctl =
ldst_cmd.u.mps.rplc.fid_idx =
htons(FW_LDST_CMD_FID_V(FW_LDST_MPS_RPLC) |
FW_LDST_CMD_CTL_V(idx));
FW_LDST_CMD_IDX_V(idx));
ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd,
sizeof(ldst_cmd), &ldst_cmd);
if (ret)
dev_warn(adap->pdev_dev, "Can't read MPS "
"replication map for idx %d: %d\n",
idx, -ret);
else {
rplc[0] = ntohl(ldst_cmd.u.mps.rplc31_0);
rplc[1] = ntohl(ldst_cmd.u.mps.rplc63_32);
rplc[2] = ntohl(ldst_cmd.u.mps.rplc95_64);
rplc[3] = ntohl(ldst_cmd.u.mps.rplc127_96);
mps_rplc = ldst_cmd.u.mps.rplc;
rplc[0] = ntohl(mps_rplc.rplc31_0);
rplc[1] = ntohl(mps_rplc.rplc63_32);
rplc[2] = ntohl(mps_rplc.rplc95_64);
rplc[3] = ntohl(mps_rplc.rplc127_96);
if (adap->params.arch.mps_rplc_size > 128) {
rplc[4] = ntohl(mps_rplc.rplc159_128);
rplc[5] = ntohl(mps_rplc.rplc191_160);
rplc[6] = ntohl(mps_rplc.rplc223_192);
rplc[7] = ntohl(mps_rplc.rplc255_224);
}
}
}

tcamxy2valmask(tcamx, tcamy, addr, &mask);
seq_printf(seq, "%3u %02x:%02x:%02x:%02x:%02x:%02x %012llx"
"%3c %#x%4u%4d",
idx, addr[0], addr[1], addr[2], addr[3], addr[4],
addr[5], (unsigned long long)mask,
(cls_lo & SRAM_VLD_F) ? 'Y' : 'N', PORTMAP_G(cls_hi),
PF_G(cls_lo),
(cls_lo & VF_VALID_F) ? VF_G(cls_lo) : -1);
if (cls_lo & REPLICATE_F)
seq_printf(seq, " %08x %08x %08x %08x",
rplc[3], rplc[2], rplc[1], rplc[0]);
if (chip_ver > CHELSIO_T5)
seq_printf(seq, "%3u %02x:%02x:%02x:%02x:%02x:%02x "
"%012llx%3c %#x%4u%4d",
idx, addr[0], addr[1], addr[2], addr[3],
addr[4], addr[5], (unsigned long long)mask,
(cls_lo & T6_SRAM_VLD_F) ? 'Y' : 'N',
PORTMAP_G(cls_hi),
T6_PF_G(cls_lo),
(cls_lo & T6_VF_VALID_F) ?
T6_VF_G(cls_lo) : -1);
else
seq_printf(seq, "%36c", ' ');
seq_printf(seq, "%4u%3u%3u%3u %#x\n",
SRAM_PRIO0_G(cls_lo), SRAM_PRIO1_G(cls_lo),
SRAM_PRIO2_G(cls_lo), SRAM_PRIO3_G(cls_lo),
(cls_lo >> MULTILISTEN0_S) & 0xf);
seq_printf(seq, "%3u %02x:%02x:%02x:%02x:%02x:%02x "
"%012llx%3c %#x%4u%4d",
idx, addr[0], addr[1], addr[2], addr[3],
addr[4], addr[5], (unsigned long long)mask,
(cls_lo & SRAM_VLD_F) ? 'Y' : 'N',
PORTMAP_G(cls_hi),
PF_G(cls_lo),
(cls_lo & VF_VALID_F) ? VF_G(cls_lo) : -1);

if (replicate) {
if (adap->params.arch.mps_rplc_size > 128)
seq_printf(seq, " %08x %08x %08x %08x "
"%08x %08x %08x %08x",
rplc[7], rplc[6], rplc[5], rplc[4],
rplc[3], rplc[2], rplc[1], rplc[0]);
else
seq_printf(seq, " %08x %08x %08x %08x",
rplc[3], rplc[2], rplc[1], rplc[0]);
} else {
if (adap->params.arch.mps_rplc_size > 128)
seq_printf(seq, "%72c", ' ');
else
seq_printf(seq, "%36c", ' ');
}

if (chip_ver > CHELSIO_T5)
seq_printf(seq, "%4u%3u%3u%3u %#x\n",
T6_SRAM_PRIO0_G(cls_lo),
T6_SRAM_PRIO1_G(cls_lo),
T6_SRAM_PRIO2_G(cls_lo),
T6_SRAM_PRIO3_G(cls_lo),
(cls_lo >> T6_MULTILISTEN0_S) & 0xf);
else
seq_printf(seq, "%4u%3u%3u%3u %#x\n",
SRAM_PRIO0_G(cls_lo), SRAM_PRIO1_G(cls_lo),
SRAM_PRIO2_G(cls_lo), SRAM_PRIO3_G(cls_lo),
(cls_lo >> MULTILISTEN0_S) & 0xf);
}
out: return 0;
}
Expand Down Expand Up @@ -1416,6 +1503,9 @@ static int rss_config_show(struct seq_file *seq, void *v)
seq_printf(seq, " HashDelay: %3d\n", HASHDELAY_G(rssconf));
if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
seq_printf(seq, " VfWrAddr: %3d\n", VFWRADDR_G(rssconf));
else
seq_printf(seq, " VfWrAddr: %3d\n",
T6_VFWRADDR_G(rssconf));
seq_printf(seq, " KeyMode: %s\n", keymode[KEYMODE_G(rssconf)]);
seq_printf(seq, " VfWrEn: %3s\n", yesno(rssconf & VFWREN_F));
seq_printf(seq, " KeyWrEn: %3s\n", yesno(rssconf & KEYWREN_F));
Expand Down Expand Up @@ -1634,14 +1724,14 @@ static int rss_vf_config_open(struct inode *inode, struct file *file)
struct adapter *adapter = inode->i_private;
struct seq_tab *p;
struct rss_vf_conf *vfconf;
int vf;
int vf, vfcount = adapter->params.arch.vfcount;

p = seq_open_tab(file, 128, sizeof(*vfconf), 1, rss_vf_config_show);
p = seq_open_tab(file, vfcount, sizeof(*vfconf), 1, rss_vf_config_show);
if (!p)
return -ENOMEM;

vfconf = (struct rss_vf_conf *)p->data;
for (vf = 0; vf < 128; vf++) {
for (vf = 0; vf < vfcount; vf++) {
t4_read_rss_vf_config(adapter, vf, &vfconf[vf].rss_vf_vfl,
&vfconf[vf].rss_vf_vfh);
}
Expand Down Expand Up @@ -2033,7 +2123,7 @@ void add_debugfs_files(struct adapter *adap,
int t4_setup_debugfs(struct adapter *adap)
{
int i;
u32 size;
u32 size = 0;
struct dentry *de;

static struct t4_debugfs_entry t4_debugfs_files[] = {
Expand Down Expand Up @@ -2104,12 +2194,7 @@ int t4_setup_debugfs(struct adapter *adap)
size = t4_read_reg(adap, MA_EDRAM1_BAR_A);
add_debugfs_mem(adap, "edc1", MEM_EDC1, EDRAM1_SIZE_G(size));
}
if (is_t4(adap->params.chip)) {
size = t4_read_reg(adap, MA_EXT_MEMORY_BAR_A);
if (i & EXT_MEM_ENABLE_F)
add_debugfs_mem(adap, "mc", MEM_MC,
EXT_MEM_SIZE_G(size));
} else {
if (is_t5(adap->params.chip)) {
if (i & EXT_MEM0_ENABLE_F) {
size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A);
add_debugfs_mem(adap, "mc0", MEM_MC0,
Expand All @@ -2120,6 +2205,11 @@ int t4_setup_debugfs(struct adapter *adap)
add_debugfs_mem(adap, "mc1", MEM_MC1,
EXT_MEM1_SIZE_G(size));
}
} else {
if (i & EXT_MEM_ENABLE_F)
size = t4_read_reg(adap, MA_EXT_MEMORY_BAR_A);
add_debugfs_mem(adap, "mc", MEM_MC,
EXT_MEM_SIZE_G(size));
}

de = debugfs_create_file_size("flash", S_IRUSR, adap->debugfs_root, adap,
Expand Down
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