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nucleol552ze: implementation with CLOCK, LED, and UART
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| Original file line number | Diff line number | Diff line change |
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| @@ -0,0 +1,45 @@ | ||
| // +build nucleol552ze | ||
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| package machine | ||
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| import ( | ||
| "device/stm32" | ||
| "runtime/interrupt" | ||
| ) | ||
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| const ( | ||
| LED = LED_BUILTIN | ||
| LED_BUILTIN = LED_GREEN | ||
| LED_GREEN = PC7 | ||
| LED_BLUE = PB7 | ||
| LED_RED = PA9 | ||
| ) | ||
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| const ( | ||
| BUTTON = BUTTON_USER | ||
| BUTTON_USER = PC13 | ||
| ) | ||
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| // UART pins | ||
| const ( | ||
| // PG7 and PG8 are connected to the ST-Link Virtual Com Port (VCP) | ||
| UART_TX_PIN = PG7 | ||
| UART_RX_PIN = PG8 | ||
| UART_ALT_FN = 8 // GPIO_AF8_LPUART1 | ||
| ) | ||
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| var ( | ||
| // LPUART1 is the hardware serial port connected to the onboard ST-LINK | ||
| // debugger to be exposed as virtual COM port over USB on Nucleo boards. | ||
| // Both UART0 and UART1 refer to LPUART1. | ||
| UART0 = UART{ | ||
| Buffer: NewRingBuffer(), | ||
| Bus: stm32.LPUART1, | ||
| AltFuncSelector: UART_ALT_FN, | ||
| } | ||
| UART1 = &UART0 | ||
| ) | ||
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| func init() { | ||
| UART0.Interrupt = interrupt.New(stm32.IRQ_LPUART1, UART0.handleInterrupt) | ||
| } |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,62 @@ | ||
| // +build stm32,stm32l5x2 | ||
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| package machine | ||
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| // Peripheral abstraction layer for UARTs on the stm32 family. | ||
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| import ( | ||
| "device/stm32" | ||
| "runtime/interrupt" | ||
| "unsafe" | ||
| ) | ||
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| // Configure the UART. | ||
| func (uart UART) Configure(config UARTConfig) { | ||
| // Default baud rate to 115200. | ||
| if config.BaudRate == 0 { | ||
| config.BaudRate = 115200 | ||
| } | ||
|
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| // Set the GPIO pins to defaults if they're not set | ||
| if config.TX == 0 && config.RX == 0 { | ||
| config.TX = UART_TX_PIN | ||
| config.RX = UART_RX_PIN | ||
| } | ||
|
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| // Enable USART clock | ||
| enableAltFuncClock(unsafe.Pointer(uart.Bus)) | ||
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| uart.configurePins(config) | ||
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| // Set baud rate | ||
| uart.SetBaudRate(config.BaudRate) | ||
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| // Enable USART port, tx, rx and rx interrupts | ||
| uart.Bus.CR1.Set(stm32.USART_CR1_TE | stm32.USART_CR1_RE | stm32.USART_CR1_RXNEIE | stm32.USART_CR1_UE) | ||
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| // Enable RX IRQ | ||
| uart.Interrupt.SetPriority(0xc0) | ||
| uart.Interrupt.Enable() | ||
| } | ||
|
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| // handleInterrupt should be called from the appropriate interrupt handler for | ||
| // this UART instance. | ||
| func (uart *UART) handleInterrupt(interrupt.Interrupt) { | ||
| uart.Receive(byte((uart.Bus.RDR.Get() & 0xFF))) | ||
| } | ||
|
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| // SetBaudRate sets the communication speed for the UART. Defer to chip-specific | ||
| // routines for calculation | ||
| func (uart UART) SetBaudRate(br uint32) { | ||
| divider := uart.getBaudRateDivisor(br) | ||
| uart.Bus.BRR.Set(divider) | ||
| } | ||
|
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| // WriteByte writes a byte of data to the UART. | ||
| func (uart UART) WriteByte(c byte) error { | ||
| uart.Bus.TDR.Set(uint32(c)) | ||
|
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| for !uart.Bus.ISR.HasBits(stm32.USART_ISR_TXE) { | ||
| } | ||
| return nil | ||
| } |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1,4 +1,4 @@ | ||
| // +build stm32,!stm32f7x2 | ||
| // +build stm32,!stm32f7x2,!stm32l5x2 | ||
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| package machine | ||
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1,4 +1,4 @@ | ||
| // +build stm32,!stm32f7,!stm32l0 | ||
| // +build stm32,!stm32f7,!stm32l5x2,!stm32l0 | ||
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| package machine | ||
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| Original file line number | Diff line number | Diff line change |
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| @@ -0,0 +1,253 @@ | ||
| // +build stm32l5 | ||
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| package machine | ||
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| // Peripheral abstraction layer for the stm32l5 | ||
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| import ( | ||
| "device/stm32" | ||
| "unsafe" | ||
| ) | ||
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| const ( | ||
| PA0 = portA + 0 | ||
| PA1 = portA + 1 | ||
| PA2 = portA + 2 | ||
| PA3 = portA + 3 | ||
| PA4 = portA + 4 | ||
| PA5 = portA + 5 | ||
| PA6 = portA + 6 | ||
| PA7 = portA + 7 | ||
| PA8 = portA + 8 | ||
| PA9 = portA + 9 | ||
| PA10 = portA + 10 | ||
| PA11 = portA + 11 | ||
| PA12 = portA + 12 | ||
| PA13 = portA + 13 | ||
| PA14 = portA + 14 | ||
| PA15 = portA + 15 | ||
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| PB0 = portB + 0 | ||
| PB1 = portB + 1 | ||
| PB2 = portB + 2 | ||
| PB3 = portB + 3 | ||
| PB4 = portB + 4 | ||
| PB5 = portB + 5 | ||
| PB6 = portB + 6 | ||
| PB7 = portB + 7 | ||
| PB8 = portB + 8 | ||
| PB9 = portB + 9 | ||
| PB10 = portB + 10 | ||
| PB11 = portB + 11 | ||
| PB12 = portB + 12 | ||
| PB13 = portB + 13 | ||
| PB14 = portB + 14 | ||
| PB15 = portB + 15 | ||
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| PC0 = portC + 0 | ||
| PC1 = portC + 1 | ||
| PC2 = portC + 2 | ||
| PC3 = portC + 3 | ||
| PC4 = portC + 4 | ||
| PC5 = portC + 5 | ||
| PC6 = portC + 6 | ||
| PC7 = portC + 7 | ||
| PC8 = portC + 8 | ||
| PC9 = portC + 9 | ||
| PC10 = portC + 10 | ||
| PC11 = portC + 11 | ||
| PC12 = portC + 12 | ||
| PC13 = portC + 13 | ||
| PC14 = portC + 14 | ||
| PC15 = portC + 15 | ||
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| PD0 = portD + 0 | ||
| PD1 = portD + 1 | ||
| PD2 = portD + 2 | ||
| PD3 = portD + 3 | ||
| PD4 = portD + 4 | ||
| PD5 = portD + 5 | ||
| PD6 = portD + 6 | ||
| PD7 = portD + 7 | ||
| PD8 = portD + 8 | ||
| PD9 = portD + 9 | ||
| PD10 = portD + 10 | ||
| PD11 = portD + 11 | ||
| PD12 = portD + 12 | ||
| PD13 = portD + 13 | ||
| PD14 = portD + 14 | ||
| PD15 = portD + 15 | ||
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| PE0 = portE + 0 | ||
| PE1 = portE + 1 | ||
| PE2 = portE + 2 | ||
| PE3 = portE + 3 | ||
| PE4 = portE + 4 | ||
| PE5 = portE + 5 | ||
| PE6 = portE + 6 | ||
| PE7 = portE + 7 | ||
| PE8 = portE + 8 | ||
| PE9 = portE + 9 | ||
| PE10 = portE + 10 | ||
| PE11 = portE + 11 | ||
| PE12 = portE + 12 | ||
| PE13 = portE + 13 | ||
| PE14 = portE + 14 | ||
| PE15 = portE + 15 | ||
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| PF0 = portF + 0 | ||
| PF1 = portF + 1 | ||
| PF2 = portF + 2 | ||
| PF3 = portF + 3 | ||
| PF4 = portF + 4 | ||
| PF5 = portF + 5 | ||
| PF6 = portF + 6 | ||
| PF7 = portF + 7 | ||
| PF8 = portF + 8 | ||
| PF9 = portF + 9 | ||
| PF10 = portF + 10 | ||
| PF11 = portF + 11 | ||
| PF12 = portF + 12 | ||
| PF13 = portF + 13 | ||
| PF14 = portF + 14 | ||
| PF15 = portF + 15 | ||
|
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| PG0 = portG + 0 | ||
| PG1 = portG + 1 | ||
| PG2 = portG + 2 | ||
| PG3 = portG + 3 | ||
| PG4 = portG + 4 | ||
| PG5 = portG + 5 | ||
| PG6 = portG + 6 | ||
| PG7 = portG + 7 | ||
| PG8 = portG + 8 | ||
| PG9 = portG + 9 | ||
| PG10 = portG + 10 | ||
| PG11 = portG + 11 | ||
| PG12 = portG + 12 | ||
| PG13 = portG + 13 | ||
| PG14 = portG + 14 | ||
| PG15 = portG + 15 | ||
|
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| PH0 = portH + 0 | ||
| PH1 = portH + 1 | ||
| ) | ||
|
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| func (p Pin) getPort() *stm32.GPIO_Type { | ||
| switch p / 16 { | ||
| case 0: | ||
| return stm32.GPIOA | ||
| case 1: | ||
| return stm32.GPIOB | ||
| case 2: | ||
| return stm32.GPIOC | ||
| case 3: | ||
| return stm32.GPIOD | ||
| case 4: | ||
| return stm32.GPIOE | ||
| case 5: | ||
| return stm32.GPIOF | ||
| case 6: | ||
| return stm32.GPIOG | ||
| case 7: | ||
| return stm32.GPIOH | ||
| default: | ||
| panic("machine: unknown port") | ||
| } | ||
| } | ||
|
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| // enableClock enables the clock for this desired GPIO port. | ||
| func (p Pin) enableClock() { | ||
| switch p / 16 { | ||
| case 0: | ||
| stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIOAEN) | ||
| case 1: | ||
| stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIOBEN) | ||
| case 2: | ||
| stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIOCEN) | ||
| case 3: | ||
| stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIODEN) | ||
| case 4: | ||
| stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIOEEN) | ||
| case 5: | ||
| stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIOFEN) | ||
| case 6: | ||
| stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIOGEN) | ||
| case 7: | ||
| stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIOHEN) | ||
| default: | ||
| panic("machine: unknown port") | ||
| } | ||
| } | ||
|
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| // Enable peripheral clock | ||
| func enableAltFuncClock(bus unsafe.Pointer) { | ||
| switch bus { | ||
| case unsafe.Pointer(stm32.DAC): // DAC interface clock enable | ||
| stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_DAC1EN) | ||
| case unsafe.Pointer(stm32.PWR): // Power interface clock enable | ||
| stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_PWREN) | ||
| case unsafe.Pointer(stm32.I2C3): // I2C3 clock enable | ||
| stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_I2C3EN) | ||
| case unsafe.Pointer(stm32.I2C2): // I2C2 clock enable | ||
| stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_I2C2EN) | ||
| case unsafe.Pointer(stm32.I2C1): // I2C1 clock enable | ||
| stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_I2C1EN) | ||
| case unsafe.Pointer(stm32.UART5): // UART5 clock enable | ||
| stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_UART5EN) | ||
| case unsafe.Pointer(stm32.UART4): // UART4 clock enable | ||
| stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_UART4EN) | ||
| case unsafe.Pointer(stm32.USART3): // USART3 clock enable | ||
| stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_USART3EN) | ||
| case unsafe.Pointer(stm32.USART2): // USART2 clock enable | ||
| stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_USART2EN) | ||
| case unsafe.Pointer(stm32.SPI3): // SPI3 clock enable | ||
| stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_SP3EN) | ||
| case unsafe.Pointer(stm32.SPI2): // SPI2 clock enable | ||
| stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_SPI2EN) | ||
| case unsafe.Pointer(stm32.WWDG): // Window watchdog clock enable | ||
| stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_WWDGEN) | ||
| case unsafe.Pointer(stm32.TIM7): // TIM7 clock enable | ||
| stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_TIM7EN) | ||
| case unsafe.Pointer(stm32.TIM6): // TIM6 clock enable | ||
| stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_TIM6EN) | ||
| case unsafe.Pointer(stm32.TIM5): // TIM5 clock enable | ||
| stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_TIM5EN) | ||
| case unsafe.Pointer(stm32.TIM4): // TIM4 clock enable | ||
| stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_TIM4EN) | ||
| case unsafe.Pointer(stm32.TIM3): // TIM3 clock enable | ||
| stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_TIM3EN) | ||
| case unsafe.Pointer(stm32.TIM2): // TIM2 clock enable | ||
| stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_TIM2EN) | ||
|
|
||
| case unsafe.Pointer(stm32.UCPD1): // UCPD1 clock enable | ||
| stm32.RCC.APB1ENR2.SetBits(stm32.RCC_APB1ENR2_UCPD1EN) | ||
| case unsafe.Pointer(stm32.FDCAN1): // FDCAN1 clock enable | ||
| stm32.RCC.APB1ENR2.SetBits(stm32.RCC_APB1ENR2_FDCAN1EN) | ||
| case unsafe.Pointer(stm32.LPTIM3): // LPTIM3 clock enable | ||
| stm32.RCC.APB1ENR2.SetBits(stm32.RCC_APB1ENR2_LPTIM3EN) | ||
| case unsafe.Pointer(stm32.LPTIM2): // LPTIM2 clock enable | ||
| stm32.RCC.APB1ENR2.SetBits(stm32.RCC_APB1ENR2_LPTIM2EN) | ||
| case unsafe.Pointer(stm32.I2C4): // I2C4 clock enable | ||
| stm32.RCC.APB1ENR2.SetBits(stm32.RCC_APB1ENR2_I2C4EN) | ||
| case unsafe.Pointer(stm32.LPUART1): // LPUART1 clock enable | ||
| stm32.RCC.APB1ENR2.SetBits(stm32.RCC_APB1ENR2_LPUART1EN) | ||
|
|
||
| case unsafe.Pointer(stm32.TIM17): // TIM17 clock enable | ||
| stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM17EN) | ||
| case unsafe.Pointer(stm32.TIM16): // TIM16 clock enable | ||
| stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM16EN) | ||
| case unsafe.Pointer(stm32.TIM15): // TIM15 clock enable | ||
| stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM15EN) | ||
| case unsafe.Pointer(stm32.SYSCFG): // System configuration controller clock enable | ||
| stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_SYSCFGEN) | ||
| case unsafe.Pointer(stm32.SPI1): // SPI1 clock enable | ||
| stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_SPI1EN) | ||
| case unsafe.Pointer(stm32.USART1): // USART1 clock enable | ||
| stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_USART1EN) | ||
| case unsafe.Pointer(stm32.TIM8): // TIM8 clock enable | ||
| stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM8EN) | ||
| case unsafe.Pointer(stm32.TIM1): // TIM1 clock enable | ||
| stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM1EN) | ||
| } | ||
| } |
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