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Top level design with full adder

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ECE 281 ICE 3: Ripple-Carry Adder with Top Level Design

This is a template repository.

ICE 3 instructions

Targeted toward Digilent Basys3. Make sure to install the board files.

Tested on Vivado 2024.2


GitHub Actions Testbench

The workflow uses the setup-ghdl-ci GitHub action to run a nightly build of GHDL.

First, the workflow uses GHDL to analyze all .vhd files in src/.

Then it elaborates the entity defined by $TB_ENTITY

Finally, the workflow runs the simulation. If successful then it will quietly exit with a 0 code. If any of the assert statements fail then GHDL will cease the simulation and exit with non-zero code; this will also cause the workflow to fail. Assert statements of other severity levels will be reported, but not fail the workflow.

My sketch of my top level Basys3 My waveform

##Documentation C3C Duke Harris helped me with understanding how to create my testbench correctly after not understanding how the code read the LSB/MSB, he also helped me troubleshoot my bitstream not generating after realizng the lab instructions were incorrect/incomplete and some of the provided code was also incorrect.

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