Merge branch 'master' into icache-missqueue

.github/workflows/emu.yml

@@ -70,7 +70,7 @@ jobs:
           echo $AM_HOME
           echo $NEMU_HOME
           echo $NOOP_HOME
-          make -C $AM_HOME/apps/microbench ARCH=riscv64-noop AM_HOME=$AM_HOME NEMU_HOME=$NEMU_HOME NOOP_HOME=$NOOP_HOME mainargs=test run
+          make -C $AM_HOME/apps/microbench ARCH=riscv64-noop AM_HOME=$AM_HOME NEMU_HOME=$NEMU_HOME NOOP_HOME=$NOOP_HOME mainargs=test run 2> /dev/null
 
   riscv-tests:
     runs-on: self-hosted
@@ -87,5 +87,5 @@ jobs:
           echo $NEMU_HOME
           echo $NOOP_HOME
           echo $RVTEST_HOME
-          make -C $RVTEST_HOME/isa/ SUITES+=rv64ui SUITES+=rv64um SUITES+=rv64ua NEMU_HOME=$NEMU_HOME NOOP_HOME=$NOOP_HOME noop_run
+          make -C $RVTEST_HOME/isa/ SUITES+=rv64ui SUITES+=rv64um SUITES+=rv64ua NEMU_HOME=$NEMU_HOME NOOP_HOME=$NOOP_HOME noop_run 2> /dev/null
 

.gitmodules

@@ -1,8 +1,12 @@
 [submodule "rocket-chip"]
 	path = rocket-chip
 	url = https://github.com/chipsalliance/rocket-chip.git
-	branch = 2bdb03dbca3f77ad4c378cc1b95ab4961bc1448a
+	branch = d6bd3c61993637c3f10544c59e861fae8af29f39
 [submodule "block-inclusivecache-sifive"]
 	path = block-inclusivecache-sifive
-	url = https://github.com/sifive/block-inclusivecache-sifive.git
-	branch = d4db623ff534f775ffc49f59c4a9ef24d5d759d0
+	url = https://github.com/RISCVERS/block-inclusivecache-sifive.git
+	branch = 5491dcc937ed3c6f7722bef9db448653daab75e8
+[submodule "chiseltest"]
+	path = chiseltest
+	url = https://github.com/ucb-bar/chisel-testers2.git
+	branch = 3e3ecc5b25b7b6bc48341ec07c7a54b7ad53bcb7

Makefile

@@ -70,6 +70,7 @@ VERILATOR_FLAGS = --top-module $(SIM_TOP) \
   +define+RANDOMIZE_MEM_INIT \
   $(VTHREAD_FLAGS) \
   --assert \
+  --trace \
   --savable \
   --stats-vars \
   --output-split 5000 \
@@ -96,7 +97,7 @@ $(EMU): $(EMU_MK) $(EMU_DEPS) $(EMU_HEADERS) $(REF_SO)
 ifeq ($(REMOTE),localhost)
 	CPPFLAGS=-DREF_SO=\\\"$(REF_SO)\\\" $(MAKE) VM_PARALLEL_BUILDS=1 OPT_FAST="-O3" -C $(abspath $(dir $(EMU_MK))) -f $(abspath $(EMU_MK))
 else
-	ssh -tt $(REMOTE) 'CPPFLAGS=-DREF_SO=\\\"$(REF_SO)\\\" $(MAKE) -j250 VM_PARALLEL_BUILDS=1 OPT_FAST="-O3" -C $(abspath $(dir $(EMU_MK))) -f $(abspath $(EMU_MK))'
+	ssh -tt $(REMOTE) 'CPPFLAGS=-DREF_SO=\\\"$(REF_SO)\\\" $(MAKE) -j80 VM_PARALLEL_BUILDS=1 OPT_FAST="-O3" -C $(abspath $(dir $(EMU_MK))) -f $(abspath $(EMU_MK))'
 endif
 
 SEED ?= $(shell shuf -i 1-10000 -n 1)
@@ -132,7 +133,7 @@ clean:
 
 init:
 	git submodule update --init
-	# do not use a recursive init to pull some not used submodules
+	@# do not use a recursive init to pull some not used submodules
 	cd ./rocket-chip/ && git submodule update --init api-config-chipsalliance hardfloat
 
 .PHONY: verilog emu clean help init $(REF_SO)

build.sc

@@ -5,7 +5,7 @@ import scalalib._
 import coursier.maven.MavenRepository
 
 object CustomZincWorkerModule extends ZincWorkerModule {
-  def repositories() = Seq(
+  def repositories() = super.repositories ++ Seq(
     MavenRepository("https://maven.aliyun.com/repository/public"),
     MavenRepository("https://maven.aliyun.com/repository/apache-snapshots")
   )
@@ -25,16 +25,16 @@ trait CommonModule extends ScalaModule {
   override def scalacPluginIvyDeps = Agg(macroParadise)
 }
 
-val rocketChisel = Agg(
-  ivy"edu.berkeley.cs::chisel3:3.3.1"
+val chisel = Agg(
+  ivy"edu.berkeley.cs::chisel3:3.4.0"
 )
 
 object `rocket-chip` extends SbtModule with CommonModule {
 
   override def ivyDeps = super.ivyDeps() ++ Agg(
     ivy"${scalaOrganization()}:scala-reflect:${scalaVersion()}",
     ivy"org.json4s::json4s-jackson:3.6.1"
-  ) ++ rocketChisel
+  ) ++ chisel
 
 
   object `api-config-chipsalliance` extends CommonModule {
@@ -44,7 +44,7 @@ object `rocket-chip` extends SbtModule with CommonModule {
   object macros extends SbtModule with CommonModule
 
   object hardfloat extends SbtModule with CommonModule {
-    override def ivyDeps = super.ivyDeps() ++ rocketChisel
+    override def ivyDeps = super.ivyDeps() ++ chisel
   }
 
   override def moduleDeps = super.moduleDeps ++ Seq(
@@ -54,30 +54,42 @@ object `rocket-chip` extends SbtModule with CommonModule {
 }
 
 object `block-inclusivecache-sifive` extends CommonModule {
-  override def ivyDeps = super.ivyDeps() ++ rocketChisel
+  override def ivyDeps = super.ivyDeps() ++ chisel
 
   override def millSourcePath = super.millSourcePath / 'design / 'craft / 'inclusivecache
 
   override def moduleDeps = super.moduleDeps ++ Seq(`rocket-chip`)
 }
 
+object chiseltest extends CommonModule with SbtModule {
+  override def ivyDeps = super.ivyDeps() ++ Agg(
+	ivy"edu.berkeley.cs::treadle:1.3.0",
+	ivy"org.scalatest::scalatest:3.0.8",
+	ivy"com.lihaoyi::utest:0.7.4"
+  ) ++ chisel
+  object test extends Tests {
+	def ivyDeps = Agg(ivy"org.scalacheck::scalacheck:1.14.3")
+	def testFrameworks = Seq("org.scalatest.tools.Framework")
+  }
+}
+
 
 object XiangShan extends CommonModule with SbtModule {
   override def millSourcePath = millOuterCtx.millSourcePath
 
   override def forkArgs = Seq("-Xmx10G")
 
-  override def ivyDeps = super.ivyDeps() ++ Agg(
-    ivy"edu.berkeley.cs::chisel3:3.3.2"
+  override def ivyDeps = super.ivyDeps() ++ chisel
+  override def moduleDeps = super.moduleDeps ++ Seq(
+    `rocket-chip`, 
+	`block-inclusivecache-sifive`,
+	chiseltest
   )
 
-  override def moduleDeps = super.moduleDeps ++ Seq(`rocket-chip`, `block-inclusivecache-sifive`)
-
   object test extends Tests {
     override def ivyDeps = super.ivyDeps() ++ Agg(
       ivy"org.scalatest::scalatest:3.0.4",
       ivy"edu.berkeley.cs::chisel-iotesters:1.2+",
-      ivy"edu.berkeley.cs::chiseltest:0.2.1"
     )
 
     def testFrameworks = Seq(

debug/Makefile

@@ -25,9 +25,7 @@ cpu:
 # ------------------------------------------------------------------
 
 cputest:
-	$(MAKE) -C $(AM_HOME)/tests/cputest $(ARCH) $(EMU_ARGS) run 2>&1 | tee > cpu.log
-	cat cpu.log | grep different
-	cat cpu.log | grep IPC
+	bash cputest.sh
 
 # bputest:
 # 	$(MAKE) -C $(AM_HOME)/tests/bputest $(ARCH) run 2>&1 | tee > bpu.log
@@ -97,11 +95,10 @@ disassemble-xv6:
 	cp $(XV6_HOME)/build/code.txt ./d-xv6.log
 
 
-P = 4
-SUITE = xiangshan.backend.exu.AluTest
+SUITE = cache.L2CacheTest
 
 unit-test:
-	cd .. && mill XiangShan.test.testOnly -o -s $(SUITE) -P$(P)
+	cd .. && mill XiangShan.test.testOnly -o -s $(SUITE)
 
 unit-test-all:
 	cd .. && mill XiangShan.test.test -P$(P)

src/main/scala/utils/CircularQueuePtr.scala

@@ -0,0 +1,69 @@
+package utils
+
+import chisel3._
+import chisel3.util._
+
+class CircularQueuePtr(val entries: Int) extends Bundle {
+  val PTR_WIDTH = log2Up(entries)
+
+  val flag = Bool()
+  val value = UInt(PTR_WIDTH.W)
+
+  override def toPrintable: Printable = {
+    p"$flag:$value"
+  }
+}
+
+trait HasCircularQueuePtrHelper {
+
+  implicit class QueuePtrHelper[T <: CircularQueuePtr](ptr: T) {
+
+    final def +(v: UInt): T = {
+      val entries = ptr.entries
+      val new_ptr = Wire(ptr.cloneType)
+      if(isPow2(entries)){
+        new_ptr := (Cat(ptr.flag, ptr.value) + v).asTypeOf(new_ptr)
+      } else {
+        val new_value = ptr.value +& v
+        val diff = Cat(0.U(1.W), new_value).asSInt() - Cat(0.U(1.W), entries.U.asTypeOf(new_value)).asSInt()
+        val reverse_flag = diff >= 0.S
+        new_ptr.flag := Mux(reverse_flag, !ptr.flag, ptr.flag)
+        new_ptr.value := Mux(reverse_flag,
+          diff.asUInt(),
+          new_value
+        )
+      }
+      new_ptr
+    }
+
+    final def -(v: UInt): T = {
+      val flipped_new_ptr = ptr + (ptr.entries.U - v)
+      val new_ptr = Wire(ptr.cloneType)
+      new_ptr.flag := !flipped_new_ptr.flag
+      new_ptr.value := flipped_new_ptr.value
+      new_ptr
+    }
+
+    final def === (that_ptr: T): Bool = ptr.asUInt()===that_ptr.asUInt()
+  }
+
+
+  def isEmpty[T <: CircularQueuePtr](enq_ptr: T, deq_ptr: T): Bool = {
+    enq_ptr === deq_ptr
+  }
+
+  def isFull[T <: CircularQueuePtr](enq_ptr: T, deq_ptr: T): Bool = {
+    (enq_ptr.flag =/= deq_ptr.flag) && (enq_ptr.value === deq_ptr.value)
+  }
+
+  def distanceBetween[T <: CircularQueuePtr](enq_ptr: T, deq_ptr: T): UInt = {
+    assert(enq_ptr.entries == deq_ptr.entries)
+    Mux(enq_ptr.flag === deq_ptr.flag,
+      enq_ptr.value - deq_ptr.value,
+      enq_ptr.entries.U + enq_ptr.value - deq_ptr.value)
+  }
+
+  def isAfter[T <: CircularQueuePtr](left: T, right: T): Bool = {
+    Mux(left.flag === right.flag, left.value > right.value, left.value < right.value)
+  }
+}

src/main/scala/xiangshan/Bundle.scala

@@ -5,6 +5,8 @@ import chisel3.util._
 import bus.simplebus._
 import xiangshan.backend.brq.BrqPtr
 import xiangshan.backend.rename.FreeListPtr
+import xiangshan.backend.roq.RoqPtr
+import xiangshan.mem.{LqPtr, SqPtr}
 import xiangshan.frontend.PreDecodeInfo
 import xiangshan.frontend.HasBPUParameter
 import xiangshan.frontend.HasTageParameter
@@ -139,35 +141,34 @@ class CfCtrl extends XSBundle {
   val brTag = new BrqPtr
 }
 
-trait HasRoqIdx { this: HasXSParameter =>
-  val roqIdx = UInt(RoqIdxWidth.W)
-
-  def isAfter(thatIdx: UInt): Bool = {
-    Mux(
-      this.roqIdx.head(1) === thatIdx.head(1),
-      this.roqIdx.tail(1) > thatIdx.tail(1),
-      this.roqIdx.tail(1) < thatIdx.tail(1)
-    )
-  }
-
-  def isAfter[ T<: HasRoqIdx ](that: T): Bool = {
-    isAfter(that.roqIdx)
-  }
-
-  def needFlush(redirect: Valid[Redirect]): Bool = {
-    redirect.valid && (redirect.bits.isException || redirect.bits.isFlushPipe || this.isAfter(redirect.bits.roqIdx)) // TODO: need check by JiaWei
-  }
+// Load / Store Index
+//
+// When using unified lsroq, lsIdx serves as lsroqIdx,
+// while separated lq and sq is used, lsIdx consists of lqIdx, sqIdx and l/s type.
+// All lsroqIdx will be replaced by new lsIdx in the future.
+trait HasLSIdx { this: HasXSParameter =>
+
+  // if(EnableUnifiedLSQ){
+  // Unified LSQ
+  val lsroqIdx = UInt(LsroqIdxWidth.W)
+  // } else {
+  // Separate LSQ
+  val lqIdx = new LqPtr
+  val sqIdx = new SqPtr
 }
 
+class LSIdx extends XSBundle with HasLSIdx {}
+
 // CfCtrl -> MicroOp at Rename Stage
-class MicroOp extends CfCtrl with HasRoqIdx {
+class MicroOp extends CfCtrl with HasLSIdx {
   val psrc1, psrc2, psrc3, pdest, old_pdest = UInt(PhyRegIdxWidth.W)
   val src1State, src2State, src3State = SrcState()
-  val lsroqIdx = UInt(LsroqIdxWidth.W)
+  val roqIdx = new RoqPtr
   val diffTestDebugLrScValid = Bool()
 }
 
-class Redirect extends XSBundle with HasRoqIdx {
+class Redirect extends XSBundle {
+  val roqIdx = new RoqPtr
   val isException = Bool()
   val isMisPred = Bool()
   val isReplay = Bool()
@@ -224,7 +225,8 @@ class RoqCommit extends XSBundle {
   val isWalk = Bool()
 }
 
-class TlbFeedback extends XSBundle with HasRoqIdx{
+class TlbFeedback extends XSBundle {
+  val roqIdx = new RoqPtr
   val hit = Bool()
 }
 

src/main/scala/xiangshan/XSCore.scala

@@ -47,20 +47,23 @@ case class XSCoreParameters
   DecodeWidth: Int = 6,
   RenameWidth: Int = 6,
   CommitWidth: Int = 6,
-  BrqSize: Int = 16,
+  BrqSize: Int = 12,
   IssQueSize: Int = 8,
-  NRPhyRegs: Int = 128,
+  NRPhyRegs: Int = 72,
   NRIntReadPorts: Int = 8,
   NRIntWritePorts: Int = 8,
   NRFpReadPorts: Int = 14,
-  NRFpWritePorts: Int = 8,
+  NRFpWritePorts: Int = 8, 
+  EnableUnifiedLSQ: Boolean = false,
   LsroqSize: Int = 16,
+  LoadQueueSize: Int = 12,
+  StoreQueueSize: Int = 10,
   RoqSize: Int = 32,
   dpParams: DispatchParameters = DispatchParameters(
     DqEnqWidth = 4,
-    IntDqSize = 64,
-    FpDqSize = 64,
-    LsDqSize = 64,
+    IntDqSize = 24,
+    FpDqSize = 16,
+    LsDqSize = 16,
     IntDqDeqWidth = 4,
     FpDqDeqWidth = 4,
     LsDqDeqWidth = 4,
@@ -137,12 +140,13 @@ trait HasXSParameter {
   val BrTagWidth = log2Up(BrqSize)
   val NRPhyRegs = core.NRPhyRegs
   val PhyRegIdxWidth = log2Up(NRPhyRegs)
-  val LsroqSize = core.LsroqSize // 64
   val RoqSize = core.RoqSize
-  val InnerRoqIdxWidth = log2Up(RoqSize)
-  val RoqIdxWidth = InnerRoqIdxWidth + 1
+  val EnableUnifiedLSQ = core.EnableUnifiedLSQ
+  val LsroqSize = core.LsroqSize // 64
   val InnerLsroqIdxWidth = log2Up(LsroqSize)
   val LsroqIdxWidth = InnerLsroqIdxWidth + 1
+  val LoadQueueSize = core.LoadQueueSize
+  val StoreQueueSize = core.StoreQueueSize
   val dpParams = core.dpParams
   val ReplayWidth = dpParams.IntDqReplayWidth + dpParams.FpDqReplayWidth + dpParams.LsDqReplayWidth
   val exuParameters = core.exuParameters

src/main/scala/xiangshan/backend/Backend.scala

@@ -210,8 +210,11 @@ class Backend extends XSModule
   roq.io.dp1Req <> dispatch.io.toRoq
   dispatch.io.roqIdxs <> roq.io.roqIdxs
   io.mem.dp1Req <> dispatch.io.toLsroq
-  dispatch.io.lsroqIdxs <> io.mem.lsroqIdxs
-  dispatch.io.commits <> roq.io.commits
+  dispatch.io.lsIdxs <> io.mem.lsIdxs
+  dispatch.io.dequeueRoqIndex.valid := roq.io.commitRoqIndex.valid || io.mem.oldestStore.valid
+  // store writeback must be after commit roqIdx
+  dispatch.io.dequeueRoqIndex.bits := Mux(io.mem.oldestStore.valid, io.mem.oldestStore.bits, roq.io.commitRoqIndex.bits)
+
 
   intRf.io.readPorts <> dispatch.io.readIntRf
   fpRf.io.readPorts <> dispatch.io.readFpRf ++ issueQueues.flatMap(_.io.readFpRf)