Merge pull request JuliaLang#37159 from JuliaLang/vc/llvm10-patches

[LLVM] add patches for LLVM 10

deps/llvm.mk

@@ -429,9 +429,9 @@ $(eval $(call LLVM_PATCH,llvm-9.0-D65174-limit-merge-stores)) # remove for 10.0
 $(eval $(call LLVM_PATCH,llvm9-D71443-PPC-MC-redef-symbol)) # remove for 10.0
 $(eval $(call LLVM_PATCH,llvm-9.0-D78196)) # remove for 11.0
 $(eval $(call LLVM_PATCH,llvm-julia-tsan-custom-as))
-$(eval $(call LLVM_PATCH,llvm-9.0-D85499))
-$(eval $(call LLVM_PATCH,llvm-D80101))
-$(eval $(call LLVM_PATCH,llvm-D84031))
+$(eval $(call LLVM_PATCH,llvm-9.0-D85499)) # landed as D85553
+$(eval $(call LLVM_PATCH,llvm-D80101)) # remove for LLVM 12
+$(eval $(call LLVM_PATCH,llvm-D84031)) # remove for LLVM 12
 endif # LLVM_VER 9.0
 
 ifeq ($(LLVM_VER_SHORT),10.0)
@@ -447,8 +447,11 @@ $(eval $(call LLVM_PATCH,llvm-D75072-SCEV-add-type))
 $(eval $(call LLVM_PATCH,llvm-10.0-PPC_SELECT_CC)) # delete for LLVM 11
 $(eval $(call LLVM_PATCH,llvm-10.0-PPC-LI-Elimination)) # delete for LLVM 11
 $(eval $(call LLVM_PATCH,llvm-julia-tsan-custom-as))
-$(eval $(call LLVM_PATCH,llvm-D80101))
-$(eval $(call LLVM_PATCH,llvm-D84031))
+$(eval $(call LLVM_PATCH,llvm-D80101)) # remove for LLVM 12
+$(eval $(call LLVM_PATCH,llvm-D84031)) # remove for LLVM 12
+$(eval $(call LLVM_PATCH,llvm-10-D85553)) # remove for LLVM 12
+$(eval $(call LLVM_PATCH,llvm-10-r_aarch64_prel32)) # remove for LLVM 12
+$(eval $(call LLVM_PATCH,llvm-10-r_ppc_rel)) # remove for LLVM 12
 endif # LLVM_VER 10.0
 
 ifeq ($(LLVM_VER_SHORT),11.0)
@@ -460,6 +463,9 @@ $(eval $(call LLVM_PATCH,llvm9-D50010-VNCoercion-ni))
 $(eval $(call LLVM_PATCH,llvm7-revert-D44485))
 #$(eval $(call LLVM_PATCH,llvm-D75072-SCEV-add-type))
 $(eval $(call LLVM_PATCH,llvm-julia-tsan-custom-as))
+$(eval $(call LLVM_PATCH,llvm-D80101)) # remove for LLVM 12
+$(eval $(call LLVM_PATCH,llvm-D84031)) # remove for LLVM 12
+$(eval $(call LLVM_PATCH,llvm-10-D85553)) # remove for LLVM 12
 endif # LLVM_VER 11.0
 
 

deps/patches/llvm-10-D85553.patch

@@ -0,0 +1,53 @@
+From 4d30f46738d417c305c0e748a49020d4513ac4ee Mon Sep 17 00:00:00 2001
+From: Keno Fischer <[email protected]>
+Date: Fri, 7 Aug 2020 16:38:15 -0400
+Subject: [PATCH] [X86] Don't produce bad x86andp nodes for i1 vectors
+
+In D85499, I attempted to fix this same issue by canonicalizing
+andnp for i1 vectors, but since there was some opposition to such
+a change, this commit just fixes the bug by using two different
+forms depending on which kind of vector type is in use. We can
+then always decide to switch the canonical forms later.
+
+Description of the original bug:
+We have a DAG combine that tries to fold (vselect cond, 0000..., X) -> (andnp cond, x).
+However, it does so by attempting to create an i64 vector with the number
+of elements obtained by truncating division by 64 from the bitwidth. This is
+bad for mask vectors like v8i1, since that division is just zero. Besides,
+we don't want i64 vectors anyway. For i1 vectors, switch the pattern
+to (andnp (not cond), x), which is the canonical form for `kandn`
+on mask registers.
+
+Fixes https://github.com/JuliaLang/julia/issues/36955.
+
+Differential Revision: https://reviews.llvm.org/D85553
+---
+ llvm/lib/Target/X86/X86ISelLowering.cpp | 12 ++++++++----
+ 1 file changed, 8 insertions(+), 4 deletions(-)
+
+diff --git llvm/lib/Target/X86/X86ISelLowering.cpp llvm/lib/Target/X86/X86ISelLowering.cpp
+index c8720d9ae3a..17eaa49c83f 100644
+--- llvm/lib/Target/X86/X86ISelLowering.cpp
++++ llvm/lib/Target/X86/X86ISelLowering.cpp
+@@ -37630,10 +37630,14 @@ combineVSelectWithAllOnesOrZeros(SDNode *N, SelectionDAG &DAG,
+
+   // vselect Cond, 000..., X -> andn Cond, X
+   if (TValIsAllZeros) {
+-    MVT AndNVT = MVT::getVectorVT(MVT::i64, CondVT.getSizeInBits() / 64);
+-    SDValue CastCond = DAG.getBitcast(AndNVT, Cond);
+-    SDValue CastRHS = DAG.getBitcast(AndNVT, RHS);
+-    SDValue AndN = DAG.getNode(X86ISD::ANDNP, DL, AndNVT, CastCond, CastRHS);
++    SDValue CastRHS = DAG.getBitcast(CondVT, RHS);
++    SDValue AndN;
++    // The canonical form differs for i1 vectors - x86andnp is not used
++    if (CondVT.getScalarType() == MVT::i1)
++      AndN = DAG.getNode(ISD::AND, DL, CondVT, DAG.getNOT(DL, Cond, CondVT),
++                         CastRHS);
++    else
++      AndN = DAG.getNode(X86ISD::ANDNP, DL, CondVT, Cond, CastRHS);
+     return DAG.getBitcast(VT, AndN);
+   }
+
+-- 
+2.28.0
+

deps/patches/llvm-10-r_aarch64_prel32.patch

@@ -0,0 +1,66 @@
+From c530dd687328d4208f91e62b600d25ec6e7f0f39 Mon Sep 17 00:00:00 2001
+From: Fangrui Song <[email protected]>
+Date: Fri, 17 Jul 2020 23:49:15 -0700
+Subject: [PATCH 2/2] [RelocationResolver] Support R_AARCH64_PREL32
+
+Code from D83800 by Yichao Yu
+---
+ llvm/lib/Object/RelocationResolver.cpp  |  6 ++++++
+ llvm/test/DebugInfo/AArch64/eh-frame.ll | 21 +++++++++++++++++++++
+ 2 files changed, 27 insertions(+)
+ create mode 100644 llvm/test/DebugInfo/AArch64/eh-frame.ll
+
+diff --git llvm/lib/Object/RelocationResolver.cpp llvm/lib/Object/RelocationResolver.cpp
+index eedb236f83d..80339ebf7b9 100644
+--- llvm/lib/Object/RelocationResolver.cpp
++++ llvm/lib/Object/RelocationResolver.cpp
+@@ -62,6 +62,8 @@ static bool supportsAArch64(uint64_t Type) {
+   switch (Type) {
+   case ELF::R_AARCH64_ABS32:
+   case ELF::R_AARCH64_ABS64:
++  case ELF::R_AARCH64_PREL32:
++  case ELF::R_AARCH64_PREL64:
+     return true;
+   default:
+     return false;
+@@ -74,6 +76,10 @@ static uint64_t resolveAArch64(RelocationRef R, uint64_t S, uint64_t A) {
+     return (S + getELFAddend(R)) & 0xFFFFFFFF;
+   case ELF::R_AARCH64_ABS64:
+     return S + getELFAddend(R);
++  case ELF::R_AARCH64_PREL32:
++    return (S + getELFAddend(R) - R.getOffset()) & 0xFFFFFFFF;
++  case ELF::R_AARCH64_PREL64:
++    return S + getELFAddend(R) - R.getOffset();
+   default:
+     llvm_unreachable("Invalid relocation type");
+   }
+diff --git llvm/test/DebugInfo/AArch64/eh-frame.ll llvm/test/DebugInfo/AArch64/eh-frame.ll
+new file mode 100644
+index 00000000000..9651159271e
+--- /dev/null
++++ llvm/test/DebugInfo/AArch64/eh-frame.ll
+@@ -0,0 +1,21 @@
++; RUN: llc -filetype=obj -mtriple=aarch64 %s -o %t.o
++; RUN: llvm-readobj -r %t.o | FileCheck %s --check-prefix=REL32
++; RUN: llvm-dwarfdump --eh-frame %t.o 2>&1 | FileCheck %s
++
++; REL32:      R_AARCH64_PREL32 .text 0x0
++; REL32-NEXT: R_AARCH64_PREL32 .text 0x4
++
++; CHECK-NOT:  warning:
++; CHECK: FDE cie=00000000 pc=00000000...00000004
++;; TODO Take relocation into consideration
++; CHECK: FDE cie=00000000 pc=00000000...00000004
++
++define void @foo() {
++entry:
++  ret void
++}
++
++define void @bar() {
++entry:
++  ret void
++}
+-- 
+2.28.0
+

deps/patches/llvm-10-r_ppc_rel.patch

@@ -0,0 +1,116 @@
+From b7f604447cbd76c803ccff5c0ff1b699b9c1504e Mon Sep 17 00:00:00 2001
+From: Fangrui Song <[email protected]>
+Date: Fri, 17 Jul 2020 23:29:50 -0700
+Subject: [PATCH 1/2] [RelocationResolver] Support R_PPC_REL32 &
+ R_PPC64_REL{32,64}
+
+This suppresses `failed to compute relocation: R_PPC_REL32, Invalid data was encountered while parsing the file`
+and its 64-bit variants when running llvm-dwarfdump on a PowerPC object file with .eh_frame
+
+Unfortunately it is difficult to test the computation:
+DWARFDataExtractor::getEncodedPointer does not use the relocated value
+and even if it does, we need to teach llvm-dwarfdump --eh-frame to do
+some linker job to report a reasonable address.
+---
+ llvm/lib/Object/RelocationResolver.cpp  | 20 +++++++++++--
+ llvm/test/DebugInfo/PowerPC/eh-frame.ll | 39 +++++++++++++++++++++++++
+ 2 files changed, 57 insertions(+), 2 deletions(-)
+ create mode 100644 llvm/test/DebugInfo/PowerPC/eh-frame.ll
+
+diff --git llvm/lib/Object/RelocationResolver.cpp llvm/lib/Object/RelocationResolver.cpp
+index 31478be7899..eedb236f83d 100644
+--- llvm/lib/Object/RelocationResolver.cpp
++++ llvm/lib/Object/RelocationResolver.cpp
+@@ -131,6 +131,8 @@ static bool supportsPPC64(uint64_t Type) {
+   switch (Type) {
+   case ELF::R_PPC64_ADDR32:
+   case ELF::R_PPC64_ADDR64:
++  case ELF::R_PPC64_REL32:
++  case ELF::R_PPC64_REL64:
+     return true;
+   default:
+     return false;
+@@ -143,6 +145,10 @@ static uint64_t resolvePPC64(RelocationRef R, uint64_t S, uint64_t A) {
+     return (S + getELFAddend(R)) & 0xFFFFFFFF;
+   case ELF::R_PPC64_ADDR64:
+     return S + getELFAddend(R);
++  case ELF::R_PPC64_REL32:
++    return (S + getELFAddend(R) - R.getOffset()) & 0xFFFFFFFF;
++  case ELF::R_PPC64_REL64:
++    return S + getELFAddend(R) - R.getOffset();
+   default:
+     llvm_unreachable("Invalid relocation type");
+   }
+@@ -238,12 +244,22 @@ static uint64_t resolveX86(RelocationRef R, uint64_t S, uint64_t A) {
+ }
+
+ static bool supportsPPC32(uint64_t Type) {
+-  return Type == ELF::R_PPC_ADDR32;
++  switch (Type) {
++  case ELF::R_PPC_ADDR32:
++  case ELF::R_PPC_REL32:
++    return true;
++  default:
++    return false;
++  }
+ }
+
+ static uint64_t resolvePPC32(RelocationRef R, uint64_t S, uint64_t A) {
+-  if (R.getType() == ELF::R_PPC_ADDR32)
++  switch (R.getType()) {
++  case ELF::R_PPC_ADDR32:
+     return (S + getELFAddend(R)) & 0xFFFFFFFF;
++  case ELF::R_PPC_REL32:
++    return (S + getELFAddend(R) - R.getOffset()) & 0xFFFFFFFF;
++  }
+   llvm_unreachable("Invalid relocation type");
+ }
+
+diff --git llvm/test/DebugInfo/PowerPC/eh-frame.ll llvm/test/DebugInfo/PowerPC/eh-frame.ll
+new file mode 100644
+index 00000000000..3a8f7df6b61
+--- /dev/null
++++ llvm/test/DebugInfo/PowerPC/eh-frame.ll
+@@ -0,0 +1,39 @@
++; RUN: llc -filetype=obj -mtriple=powerpc %s -o %t32.o
++; RUN: llvm-readobj -r %t32.o | FileCheck %s --check-prefix=PPC_REL
++; RUN: llvm-dwarfdump --eh-frame %t32.o 2>&1 | FileCheck %s --check-prefix=PPC
++
++; PPC_REL:      R_PPC_REL32 .text 0x0
++; PPC_REL-NEXT: R_PPC_REL32 .text 0x4
++
++; PPC-NOT: warning:
++; PPC: FDE cie=00000000 pc=00000000...00000004
++;; TODO Take relocation into consideration
++; PPC: FDE cie=00000000 pc=00000000...00000004
++
++; RUN: llc -filetype=obj -mtriple=ppc64 %s -o %t64.o
++; RUN: llvm-readobj -r %t64.o | FileCheck %s --check-prefix=PPC64_REL
++; RUN: llvm-dwarfdump --eh-frame %t64.o 2>&1 | FileCheck %s --check-prefix=PPC64
++
++; PPC64_REL:      R_PPC64_REL32 .text 0x0
++; PPC64_REL-NEXT: R_PPC64_REL32 .text 0x10
++
++; PPC64-NOT: warning:
++; PPC64: FDE cie=00000000 pc=00000000...00000010
++; PPC64: FDE cie=00000000 pc=00000000...00000010
++
++; RUN: llc -filetype=obj -mtriple=ppc64le -code-model=large %s -o %t64l.o
++; RUN: llvm-readobj -r %t64l.o | FileCheck %s --check-prefix=PPC64L_REL
++; RUN: llvm-dwarfdump --eh-frame %t64l.o 2>&1 | FileCheck %s --check-prefix=PPC64
++
++; PPC64L_REL:      R_PPC64_REL64 .text 0x0
++; PPC64L_REL-NEXT: R_PPC64_REL64 .text 0x10
++
++define void @foo() {
++entry:
++  ret void
++}
++
++define void @bar() {
++entry:
++  ret void
++}
+-- 
+2.28.0
+