Mastering Embedded Linux Programming Third Edition, published by Packt

💻 A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.

Connect to your VHDL simulation via JTAG! GDB <-TCP-> OpenOCD <-remote bitbang-> cosim_jtag <-VHPI or FLI-> VHDL simulator.

Connect to your GHDL simulation via JTAG! GDB <-TCP-> OpenOCD <-remote bitbang-> vhpi_jtag <-VHPI-> GHDL

💾 FreeRTOS port for the NEORV32 RISC-V Processor.

Sail RISC-V model

✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

RARS -- RISC-V Assembler and Runtime Simulator

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

This is a demo application which provides a command line interface for these 6 applications of NAFE13388 for Analog to Digital Conversion.<br>Current Sensing using SCSR Conversion Voltage Sensing u…

A fast convert library between the JSON and C structure. Implement structure serialization and deserialization for C. | C 结构体与 JSON 快速互转库，快速实现 C 结构体的序列化及反序列化

Convert JSON to C data literals

A curated list of awesome smartnic tutorials, papers and projects.

Landing page for Software for Open Networking in the Cloud (SONiC) - https://sonic-net.github.io/SONiC/

Open source drivers and initialization library for Arista platforms running SONiC

单片机APP程序

SFP module test board for Raspberry Pi Pico

Python tool for converting files and office documents to Markdown.

A graphical processor simulator and assembly editor for the RISC-V ISA

Wavious RTOS Base Software

RPL for {Linux, LWIP, Embedded OS}. A mesh routing protocol implementation designed to scale, yet resource optimal. Primary factor for optimization is to reduce network control overhead.

Main development repository for TinyOS (an OS for embedded, wireless devices).

An Open Source Link Protocol and Controller

Wavious DDR (WDDR) Physical interface (PHY) Software

Python package for design and simulation of RF phase-locked loops

RISC V emulator in JavaScript

Interactive ASCII art diagram generators. 🌟

人人都能用英语

A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence generates addresses and allows the driver to tell the BFM which …