This repository hold the CommDspy package where I implemented some signal processing procedures often used

Digital Signal Processing(DSP) Guide

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An implementation of the Multiple-Rotating-Clock-Phase Architecture for Clock and Data Recovery described by S. I. Ahmed and Tad A. Kwasniewski

A program to convert arbitrary files or data for storage on an audio cassette

Capstone project. Estimating Blood Pressure by Applying Machine Learning to PPG and ECG Signals

FTDI device driver written in pure Python

24 channel, 100Msps logic analyzer hardware and software

Cloud9 Core - Part of the Cloud9 SDK for Plugin Development https://c9.github.io/core/ https://c9.io

Custom-made draw.io-shapes - in the form of an importable library - for drawing circuits and conceptual drawings in draw.io.

🎨 Diagram as Code for prototyping cloud system architectures

Kipoi's model zoo API

Driver and GUI for LMS7002M-based SDR platforms

基于NI-VISA/VISA32(Virtual Instrument Software Architecture)的仪器编程（C#），支持RS232、USB、GPIB及LAN通信接口的收发控制

A pure Python 2/3 library for peripheral I/O (GPIO, LED, PWM, SPI, I2C, MMIO, Serial) in Linux.

A C library for peripheral I/O (GPIO, LED, PWM, SPI, I2C, MMIO, Serial) in Linux.

Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components

Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.

This is a sample project for testing C code for STM32 microcontrollers using the Google Test Framework.

WIP 100BASE-TX PHY

The Python Network Modelling Simulator

ns.py: a Pythonic Discrete-Event Network Simulator

Python Wireless Channel Simulator

Dear PyGui: A fast and powerful Graphical User Interface Toolkit for Python with minimal dependencies

TR069 server for QuecPython

A SystemVerilog implementation of a Ethernet Repeater targeting a Terasic DE2-115 and Marvell 88E1111 PHY

final project