GitHub - JustinWeidmann/Verilog_Alarm_Clock: Created a alarm clock in Verilog written for the DE0-CV Intel FPGA boards. The clock is output to the 7-segment displays and the alarm is indicated via led 1 blinking.

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Created a alarm clock in Verilog written for the DE0-CV Intel FPGA boards. The clock is output to the 7-segment displays and the alarm is indicated via led 1 blinking.

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Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
c5_pin_model_dump.txt		c5_pin_model_dump.txt
counter13.sv		counter13.sv
decimalSplitter.sv		decimalSplitter.sv
hdis.sv		hdis.sv
lab03.qpf		lab03.qpf
lab03.qsf		lab03.qsf
lab03.qws		lab03.qws
lab03.sv		lab03.sv
lab03.sv.bak		lab03.sv.bak
lab03_assignment_defaults.qdf		lab03_assignment_defaults.qdf
mydff.sv		mydff.sv
timePiece.sv		timePiece.sv
timePiece.sv.bak		timePiece.sv.bak

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Created a alarm clock in Verilog written for the DE0-CV Intel FPGA boards. The clock is output to the 7-segment displays and the alarm is indicated via led 1 blinking.

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