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Commits on Jul 14, 2021

• [formal] Read Verilog files in Yosys

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• [formal] Switch to new top level

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Commits on Jan 19, 2021

• [dv] Verilator unused parameter handling

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• [rtl] Add B extension to misa

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Commits on Jan 11, 2021

• [rtl] Avoid latch creation

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• [rtl] Use tracer parameters for decoding

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• [rtl] Disable definition of unused instructions

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• [rtl] Remove unused tracer branch instruction

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Commits on Oct 19, 2020

• Add support for additional HW breakpoints

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Commits on Oct 13, 2020

• [rtl] Add plusarg to disable trace log

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Commits on Sep 29, 2020

• [doc] Fix image link

  

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Commits on Sep 16, 2020

• [formal] Add check for multdiv cycle consumption

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• Move sv2v script into standalone core file

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Commits on May 25, 2020

• [rtl] Remove redundant assignment

  

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• [rtl] Update RVFI order

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• [rtl] Forward register data with status

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• [rtl] Set RVFI program counter

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• [formal] Create Ibex Verilog source

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• [rtl] Add RVFI IXL interface

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Commits on Apr 24, 2020

• Add RV32B parameter option

  

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Commits on Feb 20, 2020

• [doc] Fix reference link

  

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• [rtl] Change misa for RV32E

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Commits on Feb 4, 2020

• Extend riscv-compliance description

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Commits on Jan 2, 2020

• [DV] Continue argument parsing

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Commits on Dec 21, 2019

• [make] Fix target reference

  

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Commits on Dec 5, 2019

• [verilator] Clarify ELF BSS handling

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Commits on Dec 4, 2019

• [examples] Fix spelling for description type

  

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Commits on Dec 2, 2019

• [examples] Add fstream header

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Commits on Nov 27, 2019

• [DV] Add Verilator memory initialization from ELF

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Commits on Nov 26, 2019

• [make] Add CS Register testbench targets

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Commits on Nov 25, 2019

• Update gitignore to include simple system files

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• Update gitignore for tag file

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Commits on Nov 20, 2019

• [make] Add Makefile for common tasks

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Commits on Nov 18, 2019

• [DV] Add exit check for setup call

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Commits on Nov 14, 2019

• Update fusesoc usage

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