This is a repository containing solutions to the problem statements given in HDL Bits website.

A hardware h264 video encoder written in VHDL. Designed to be synthesized into an FPGA. Initial testing is using Xilinx tools and FPGAs but it is not specific to Xilinx.

Xilinx QDMA IP Drivers

Open Logic FPGA Standard Library

A cross-platform, OpenGL terminal emulator.

simple terminal UI for git commands

📜 A Cheat-Sheet Collection from the WWW

My configuration files for bash, vim, tmux and so forth.

A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models

Control and Status Register map generator for HDL projects

Tri-mode (10/100/1000) full-duplex FPGA ethernet MAC in VHDL

Send video/audio over HDMI on an FPGA

Neovim plugin that evaluates code blocks inside documents

Virtual Development Board

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

Style guide enforcement for VHDL

A huge VHDL library for FPGA development

SLAC Python Based Hardware Abstraction & Data Acquisition System

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

Parallel Programming for FPGAs -- An open-source high-level synthesis book

Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog

OpenCppCoverage is an open source code coverage tool for C++ under Windows.

GoogleTest - Google Testing and Mocking Framework

Xilinx Embedded Software (embeddedsw) Development