HLS Project of pp4fpgas - https://github.com/xupsh/pp4fpgas-cn

用 Vue3 和 Go 搭建的微软 New Bing 演示站点，拥有一致的 UI 体验，支持 ChatGPT 提示词，国内可用。

Vivado诸多IP，包括图像处理等

基于Matlab的LDPC编解码算法实现及LDPC码性能测试

(RETIRED see https://github.com/analogdevicesinc/hdl instead) FPGA interface reference designs for Analog Devices mixed signal IC products

Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.

Vitis Model Composer Examples and Tutorials

SystemVerilog parser library fully compliant with IEEE 1800-2017

Verilog AXI stream components for FPGA implementation

一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。

Verilog AXI components for FPGA implementation

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

OpenTSN3.4开源项目的新特性：（1）交换平面深度解耦，硬件代码由TSS（时间敏感交换），HCP（硬件控制点）和OSMAC（Opensync MAC）实现。（2）集成了Opensync开源实现，支持802.1AS和AS6802两种时间同步协议；（3）集成了TSN硬件仿真工具OpenEmulator，用户可在仿真环境下运行OpenTSN3.4交换机、网卡、控制器和opensync同步软件

分享FPGA开发知识、优秀文章、学习网站以及开源项目。本项目收集了github中许多FPGA开源项目。

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

🐱给小白的Shadowsocks翻墙教程-Easy-to-follow tutorials for beginners on using Shadowsocks to bypass internet restrictions.

ShadowsocksR update rss, SSR organization https://github.com/shadowsocksr

翻墙 从容穿越党国敏感日 ShadowsocksR (SSRoT) native implementation for all platforms, GFW terminator

An unidentifiable mechanism that helps you bypass GFW.

翻墙-科学上网

Investigating the performance of an OFDM-based communication system with QPSK and QAM modulation and effects of AWGN and multi-path channels.

Phase Locked Loop for an I-Q modulated signal with a fixed phase offset.

A collection of phase locked loop (PLL) related projects

A robotic arm controller design based on AMD/Xilinx KR260 FPGA dev-kit.

This project's goal is to transmit picture through microphone and speaker in audio signal with minimal error rate and develop algorithms both in frequency domain and time domain to improve the accu…

16QAM modulation and demodulation by Verilog

A variable FPGA-based QAM transmitter with scalable mixed time and frequency domain signal processing.

《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS).

《MIMO-OFDM无线通信技术及MATLAB实现》随书源码