This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Networks on FPGAs

100 Days of RTL

SystemVerilog Tutorial

Like VexRiscv, but, Harder, Better, Faster, Stronger

Lab files for EE108 - Digital Systems Design, class taken in Winter/2019

Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied in the design of simple logic circuits and in the physical i…

IC implementation of TPU

My personal webpage

This repo contains an implementation of a 2x2 Systolic Array using Verilog HDL. The testbench is also included in the design file.

Convolutional accelerator kernel, target ASIC & FPGA

32-bit 5-Stage Pipelined RISC V RV32I Core

cocotb: Python-based chip verification

OpenTitan: Open source silicon root of trust

Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL

Master and Slave made using AMBA AXI4 Lite protocol.

List of Computer Science courses with video lectures.

5 Staged Pipelined RISC V Processor

This repo is created to include illustrative examples on object oriented design pattern in SV